PLC and PLD are familiar terms to most people in the control industry and microcontroller enthusiasts. Although they differ by only one word, do you know the difference? If you're interested, check out today's content.
I. A programmable logic controller (PLC) is a member of the computer family, designed and manufactured for industrial control applications. Early programmable controllers were called programmable logic controllers, or PLCs for short, and were mainly used to replace relays to implement logic control.
With the development of technology, the functions of this device have far exceeded the scope of logic control. Therefore, today this device is called a programmable logic controller, or PC for short. However, to avoid confusion with the abbreviation for personal computer, programmable logic controller is abbreviated as PLC (Programmable Logic Controller).
Internal circuit of a certain type of PLC
Main features of PLC
High reliability
Abundant I/O interface modules
Adopting a modular structure
Programming is simple and easy to learn
Easy to install and maintain
PLC functions
Logic control
Timed control
Counting control
Step (sequence) control
PID control
Data control: PLC has data processing capabilities.
Communication and networking
other
PLCs also have many special function modules suitable for various special control requirements, such as positioning control modules and CRT modules.
A certain model of PLC control cabinet
2. PLD is short for Programmable Logic Device, and FPGA is short for Field Programmable Gate Array. The two have basically the same function, but their implementation principles are slightly different. Therefore, we can sometimes ignore the difference between the two and refer to them collectively as programmable logic devices or PLD/FPGA.
PLDs are one of the most dynamic and promising technologies in the field of electronic design, and their impact is no less than that of the invention and use of microcontrollers in the 1970s. What can PLDs do? It is no exaggeration to say that PLDs can perform the functions of any digital device, from high-performance CPUs to simple 74 circuits.
A PLD (Power Delivery Logic Controller) is like a blank sheet of paper or a set of building blocks. Engineers can freely design a digital system using traditional schematic input methods or hardware description languages. Software simulation allows us to verify the correctness of the design beforehand. After the PCB is completed, the PLD's online modification capabilities allow for design changes at any time without altering the hardware circuitry. Using PLDs to develop digital circuits can significantly shorten design time, reduce PCB area, and improve system reliability.
Internal circuit of a certain type of PLD
A typical PLD consists of an AND gate and an OR gate array. Any combinational logic can be described by an AND-OR expression. Therefore, a PLD can perform a large number of combinational logic functions in the form of product sums. The products at this stage are mainly PAL (Programmable Array Logic) and GAL (General Purpose Array Logic).
With programmable logic devices (PLDs), designers can rapidly develop, simulate, and test their designs using inexpensive software tools. The design can then be quickly programmed into the device and immediately tested in a real-world circuit. The PLDs used in the prototypes are identical to those used in the final production devices, such as network routers, DSL modems, DVD players, or car navigation systems. This eliminates NRE (Network Execution Environment) costs, and the final design is completed much faster than with custom fixed logic devices.
Another key advantage of using PLDs is that customers can modify the circuitry as needed during the design phase until they are satisfied with the design. This is because PLDs are based on rewritable memory technology—to change the design, simply reprogram the devices. Once the design is complete, customers can immediately put it into production by simply programming the required number of PLDs using the final software design file.
Appearance of a certain model of PLD
The following section uses FPGA as an example to introduce the programming principles of PLD.
The programming data storage units are distributed in an array within the FPGA, as shown in Figure 1. Each storage unit is a 5-transistor SRAM structure with only one bit line. The T-transistor is the control gate for that unit, controlled by the word line. Data is serially shifted into the shift register, which sequentially selects one word line of the storage unit. When a word line is high, the T-transistor of that storage unit is turned on, connecting it to the bit line. Under the control of the write signal, the data of one word in the data shift register is written to that storage unit through the respective bit lines.
Programming data is organized into a data stream according to a specific data structure and loaded into the FPGA. The programming data stream is automatically generated by the development software. The development software converts the design into a netlist file, automatically partitions, places, and routes the logic circuits, verifies the FPGA design, then generates a programming data stream in PROM format and forms a programming data file. Finally, the programming data file can be stored in the PROM.
Figure 1 Programming data storage unit array structure
Currently, all PLD devices exceeding a certain integration level (e.g., 1000 gates or more) are generally referred to as CPLDs. A CPLD consists of programmable logic function blocks surrounding a programmable interconnect matrix. Interconnection between logic units is achieved using fixed-length metal wires, increasing the number and functionality of I/O control modules. The basic structure of a CPLD can be viewed as consisting of three parts: a programmable logic array (LAB), programmable I/O control modules, and programmable internal interconnects (PIA).
MAX7123 structure
1. Programmable Logic Array (LAB)
A programmable logic array is composed of several programmable logic macrocells (LMCs). The LMC mainly includes circuits such as AND arrays, OR arrays, programmable flip-flops, and multiplexers, which can be independently configured to operate in sequential or combinational modes.
AND-OR array structure diagram
Representation of AND and OR gates in CPLD
(1) Shared structure of product terms
In a CPLD macrocell, if there are many AND terms in the output expression and the corresponding OR gate inputs are insufficient, programmable switches can be used to combine other OR gates in the same unit (or other units) with it, or unused product terms can be provided in each macrocell for use by other macrocells.
Structure diagram of EPM7128E product term expansion and parallel expansion terms
(2) Multi-trigger structure
Early programmable devices typically had only one flip-flop per output macrocell (OLMC), while CPLDs usually contain two or more flip-flops within their macrocells. Only one of these flip-flops is connected to the output terminal, while the outputs of the remaining flip-flops are not directly connected. However, their outputs can be fed back to the AND array through appropriate buffer circuits, thus forming a more complex sequential circuit together with the other flip-flops. These internal flip-flops that are not connected to the output terminal are called "buried" flip-flops. This structure increases internal resources without increasing the number of pins.
(3) Asynchronous clock
Early programmable devices could only implement synchronous sequential circuits. In CPLD devices, the clocks of each flip-flop can operate asynchronously. In some devices, the clocks of the flip-flops can also be selected via data selectors or clock networks. Furthermore, the asynchronous clearing and asynchronous setting of flip-flops within OLMCs can be controlled using product terms, thus offering greater flexibility.
2. Programmable I/O Unit (IOC)
The I/O cell (Input/Output Cell, IOC) of a CPLD is the interface between internal signals and I/O pins. The structure varies depending on the device and its function. Since array-type devices typically have only a few dedicated input terminals, with most ports being I/O terminals, and system input signals usually need to be latched, I/O is often handled as a separate unit.
3. Programmable Internal Interconnect (PIA)
The purpose of programmable interconnects is to provide an interconnect network between logic macrocells and between logic macrocells and I/O units. Each logic macrocell receives signals from its inputs via the programmable interconnect array and sends the macrocell's signals to their destination. This interconnect mechanism offers great flexibility, allowing changes to the internal design without affecting pin assignments.
In summary, the biggest difference between the two lies in their control logic. PLCs are fixed logic devices (their functions are achieved by changing the software), while PLDs are variable logic devices (their functions are achieved by changing the internal circuit structure).
In addition, PLCs are generally used in applications where low-voltage drives require high-voltage power (automation professionals will be very familiar with this), such as the control of large machine tools and robotic arms. PLDs, on the other hand, are mainly used for early-stage integrated circuit design work, such as simulation circuits, and for low-voltage control.
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