This paper mainly introduces the electronic circuit design of a permanent magnet brushless DC motor control system based on Field-Programmable Gate Array (FPGA) and EDA methodology. FPGA is a high-density programmable logic device. Its logic functions are implemented by configuring the design-generated data file into the chip's internal static configuration data memory. It has reprogrammability and can flexibly implement various logic functions.
Unlike ASICs, PCAs are simply standard cell arrays without the functionalities of typical ICs. However, users can reprogram their internals using specialized placement and routing tools to design custom integrated circuits in the shortest possible time, significantly enhancing product competitiveness. Because it performs parallel processing in pure hardware without consuming CPU resources, it enables systems to achieve very high performance. This new design approach integrates A/D interfaces, driver interfaces, and communication interfaces onto a single chip, while simultaneously implementing position, speed, and even current algorithms, thus achieving a true System-on-a-Chip (SoPC). This will become a trend in the integrated design of next-generation high-performance servo controllers.
The following section introduces the electronic circuit design method of the control system based on FPGA, based on the modular design concept of permanent magnet brushless DC motor. The structure of the control system is shown in Figure 1.
Figure 1 Control system structure diagram
The circuit consists of a power supply module, a voltage conversion module, an FPCA module, a drive circuit module, a chopper current and voltage detection module, a winding current detection module, an A/D module, a communication module, and an external memory module.
Figure 2. Chopper inductor current detection circuit
The armature current detection signal conditioning circuit of the permanent magnet brushless DC motor and the output voltage detection signal conditioning circuit of the DC/DCBUCk converter are shown in Figures 3-16c and 3-16d, and their power circuits are shown in Figure 3.
First, the FPGA generates five PWM waves: three for commutation of the permanent magnet brushless DC motor, one for chopping, and one for regenerative braking current regulation. The three-phase commutation PWM waves control the motor's commutation via the drive circuit; these three PWM waves are only used for commutation and are not modulated, but are modulated by the chopping stage. The motor winding current is biased, amplified, and filtered before being converted by an A/D converter (ADS7864) and fed into the FPGA (XC3S200), where it is controlled by a PID controller to regulate the current loop. Similarly, the chopped voltage and current are filtered, converted by an A/D converter, and also fed into the FPGA. Figure 2 shows the minimum system circuit of FPCA. XCF02S is the configuration chip for FPGAXC3S200. TPS767D325 is the power supply chip, which converts the +5V power supply voltage to +2.5V and +3.3V to supply the FPGA. The power supply chip LM317 converts the +5V power supply voltage to +1.2V to supply the FPGA. The FPGA clock is selected as 50MHz, the crystal oscillator is a 50MHz active crystal oscillator, and the high level of the output clock signal voltage is +3.3V.
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