Abstract: The ADV202 is a real-time JPEG2000 codec chip developed by Analog Devices (AD). This paper introduces an embedded video compression system based on the ADV202 chip. This system compresses PAL/NTSC video signals into JPEG2000 standard video streams, showing broad application prospects. The hardware circuit design and software flow design of the system are discussed in detail. Keywords: JPEG2000, ADV202, embedded video compression. The JPEG2000 standard was officially launched by the International Organization for Standardization (ISO) and the International Telecommunication Union (ITU) in December 2000. This standard adopts a multi-resolution coding method based on discrete small-pass transform and has many excellent characteristics; however, it has not been widely adopted. In 2004, ADV202, a JPEG2000 codec chip capable of real-time compression and decompression of high-quality moving and still digital images, was launched by ADV202. This paper designs a complete embedded video compression system based on ADV202, including hardware circuit design and software flow design. The system has a USB interface, supports hot-swapping, and requires no host control. 1. ADV202 Chip Introduction The ADV202 is a recently launched monolithic IEC 15444-1 image compression standard codec chip from Analog Devices (ADI) for video and high-bandwidth still image compression. It is currently the only chip on the market capable of real-time compression and decompression of Standard (SD) and High Definition (HDTV) video signals. Its patented Spatial Efficient Recursive Filtering (SURF) technology enables low-power and low-cost wavelet compression. Its dedicated video interface allows seamless connection to standard digital video interfaces such as ITU-R-BT656, SMPTE125M, and SMPTE293M [525p]. Its flexible asynchronous SRAM-style host interface allows seamless connection to most 16/32-bit microcontrollers and ASIC devices. The internal functional block diagram of the ADV202 is shown in Figure 1. Input video or image data enters the video interface and is deinterleaved before being transmitted to the wavelet transform engine. In the wavelet engine, each frame of image or each patch is decomposed into many subbands through a 5/3 or 9/7 filter, and the generated wavelet coefficients are written into internal registers. The entropy encoder encodes the image data into data conforming to the JPEG2000 standard. The internal DMA engine provides high-bandwidth transfer between memory and high-performance transfer between modules and memory. The internal FIFO provides storage space for pixel data, bitstream data, feature data, and auxiliary data, which can be accessed directly by the external host through standard address read/write cycles, or through DMA using the DREQ/DACK protocol or a dedicated hardware handshake mechanism. The host interface provides a 16/32-bit control bus and an 8/16/32-bit data transmission bus for configuring, controlling, and transmitting the status of internal registers and transmitting compressed data streams. 2 Video Compression System Hardware Design 2.1 System Hardware Overall Architecture The overall system hardware framework is shown in Figure 2. Single-channel PAL/NTSC video signals from a television or camera are encoded into SAV/EAV mode and ITU-T mode by SAA7n3. The R-BT656 YUV4:2:2 format (8-bit) video signal is transmitted to the ADV202 video interface via VPO[7..0]. Inside the ADV202, the video signal is generated by hardware encoding. The .jp2 format video signal is input to the TMS320VC33 DSP via the host interface D[31..0]. The video signal compressed by the DSP is converted by the USB interface chip USBN9602 and output through the USB port. In addition, the DSP also configures the direct and indirect registers inside the ADV202 through the data bus D[31..0] and the address bus A[3..], loads the firmware required for the ADV202 encoding mode (provided by AD company), and sets the ADV202 encoding parameters. The USB port is only used as the output port of the compressed data stream and is completely controlled by the DSP. 2.2 DSP Mini-System For the sake of system ease of implementation and cost-effectiveness, the DSP chip selected is the 32-bit high-performance digital signal processor TMS320VC33 from Company II. When the TMS320VC33 operates at a 75MHz clock speed, its processing power reaches 150MFLOPS. It has a total accessible memory space of 16M×32bit, encompassing program space, data space, and I/O space, all uniformly addressed. While it provides 34K×32bit SRAM on-chip, considering the system processes video signals, requiring a larger program and data space, the on-chip RAM is often insufficient. Therefore, external memory expansion is necessary. Two CY7C1041V33 (256K×16bit) SRAM chips and one SST39VF400A (256K×16bit) FLASH chip are externally added to the DSP. The two CY7C1041V33 chips are expanded to a 256K×32bit data storage space using a data bit expansion method to store compressed video data. The DSP operates in microcomputer/boot mode (MCBL/MP=1), and the SST39VF400A is used to store the DSP's boot program. 2.3 System Timing Control Circuit The system timing control circuit is composed of an Altera EPM7128 CPLD chip, and its main functions are: (1) Expanding the DSP's general I/O pin signals XF1 and XF0 into the SCL and SDA signals required by the I2C bus, and completing the DSP's initialization settings for the SAA7113; (2) Generating the ADV202 chip select signal CS and reset signal RESET, and expanding the DSP's read/write signal R/W into the ADV202 read signal RD and write signal WE; (3) Generating the interface signals for the DSP's external memory SRAM and FLASH: address decoding strobe signal CE, write pulse signal WE, read signal OE, etc.; (4) Generating the USBN9602 interface signals: chip select signal CS, read signal RD, write signal WR, address pin signal A0. 2.4 USB Interface Design The USBN9602 is a dedicated USB interface chip from National Semiconductor, supporting the USB 1.1 standard. It has a large internal FIFO, which can cache a large amount of data, thus reducing the processor's workload. In this system, the USBN9602 is connected to the TMS320VC33 via a parallel interface. The interface signals are controlled by the CPLD. It operates in non-bus multiplexing mode (MODE0=0, MODE1=0), as shown in Figure 3. The USBN9602's operation timing is as follows: first, the address is written to the address register, and then data is read and written through the data input register and data output register. The selection of the address register and data register is implemented through AO. 2.5 Clock Signal Design This system uses three crystal oscillators. A 24.576MHz crystal oscillator provides the external clock required by the SAA7113, and a 27MHz clock output signal generated by the LLC is provided to the ADV202 encoder chip; both are powered by 5V. A 15MHz crystal oscillator is provided to the CPLD and indirectly to the DSP via the CPLD. This solves the matching problem between different voltage levels. The DSP's internal phase-locked loop uses a ×5 mode (CLKMDO=CLKMDl=1), with a working frequency of 75MHz; a 48MHz crystal oscillator provides the input clock required by the USBN9602. In the circuit board design, the clock signal should be as close as possible to the corresponding input pin. 2.6 Power Supply and System Reset Circuit Design This system requires four power supplies: 5V, 3.3V, 1.8V, and 1.5V. The 5V is provided by an external power supply, while the 3.3V, 1.8V, and 1.5V are provided by TI's TPS767D301 power supply chip via 5V conversion. The TPS767D301 can convert the 5V power input to a fixed 3.3V output and a variable output from 1.5V to 5.5V, while simultaneously generating a reset signal for the CPLD. 3. Video Compression System Software Design 3.1 System Software Flowchart and Overall Design The software design of this system mainly consists of the DSP initialization program (dspinit.c), the I2C device SAA7113 initialization program (iic.c), the ADV202 initialization program (init202.c), the DSP main control program (dspetl.c), and the USB communication software design. All these programs are completed on the DSP. Developing DSP programs using C language can shorten the development cycle, improve program development efficiency, greatly enhance program readability and portability, and provide significant convenience for system improvement and upgrades. For C language code, using an optimized compiler to generate high-efficiency assembly code can improve program execution speed and reduce the length of the target code. Therefore, the above methods were adopted in the overall design of the system software. The system software flowchart is shown in Figure 4. 3.2 Example of Main Program Implementation The ADV202 initialization program (init202.c) mainly performs the following functions: (1) Verify and configure the internal direct and indirect registers of ADV202; (2) Load the firmware program required by ADV202 in encoding mode; (3) Configure the firmware configuration register and set its working state; (4) Verify the application program ID; (5) Clear the interrupt flag to enable ADV202 to enter the running state. The ADV202 initialization flowchart is shown in Figure 5. This system has the advantages of small size, good real-time performance, and easy recovery of compressed signals. It can be widely used in non-linear editing systems, remote closed-circuit monitoring systems, video signal acquisition systems, image and video archive systems, high-quality video conferencing systems, etc. With the widespread application of ADV202, JPEG2000 technology will inevitably become one of the mainstream technologies for image and video compression in the industry.