1 Introduction Since the first digital signal processor chip (DSP) was introduced in the early 1980s, DSP has brought great opportunities to the development of digital signal processing with its unique characteristics of stability, repeatability, large-scale integration, especially programmability and easy adaptive processing. Its application fields are wide. However, since DSP is a complex, diverse, and multi-system mixed digital and analog system, the interference caused by external electromagnetic radiation and crosstalk between internal components, between subsystems and between transmission channels has seriously threatened the stability, reliability and security of its operation[1]. According to statistics, interference-induced DSP accidents account for about 90% of its total accidents. At the same time, DSP inevitably radiates electromagnetic waves, which can interfere with, hinder or damage human beings and equipment in the environment. Moreover, with the increase of DSP computing speed, the bandwidth of signals that can be processed in real time has also increased significantly, and its research focus has shifted to high-speed and real-time applications. But precisely because of this, its electromagnetic compatibility problem has become more and more prominent. This paper discusses the electromagnetic compatibility problem of DSP. 2 Electromagnetic Compatibility (EMC) of DSP Hardware Electromagnetic compatibility (EMC) encompasses both emission and sensitivity issues of a system. Even if interference cannot be completely eliminated, it should be minimized. A DSP system is considered EMC if it meets the following three conditions: (1) It does not interfere with other systems; (2) It is not sensitive to emissions from other systems; (3) It does not interfere with the system itself. 2.1 Main Sources of Interference in DSPs Electromagnetic interference is generated through conductors or through radiation. Many electromagnetic emission sources, such as light, relays, DC motors, and fluorescent lamps, can cause interference. AC power lines, interconnecting cables, metal cables, and internal circuits of subsystems can also generate radiation or receive unwanted signals. In high-speed digital circuits, clock circuits are often the biggest source of broadband noise. In fast DSP systems, these circuits can generate harmonic distortion signals up to 300MHz, which should be eliminated from the system. In digital circuits, reset lines, interrupt lines, and control lines are most susceptible to interference. 2.2 Conducted Interference in DSPs One of the most obvious propagation paths that can cause circuit noise is through conductors. A wire passing through a noisy environment can pick up noise and send it to other circuits, causing interference. Designers must avoid wires picking up noise. If noise enters the circuit through a power line, and the power supply itself or other circuits connected to it are sources of interference, the power line must be decoupled before it enters the circuit. 2.3 Common Impedance Coupling in DSP Common impedance coupling occurs when currents from two different circuits flow through a common impedance. The voltage drop across the impedance is determined by the two circuits. Ground currents from both circuits flow through the common ground impedance, the ground potential of circuit 1 is modulated by ground current 2, and noise signals or DC compensation are coupled from circuit 2 to circuit 1 through the common ground impedance. 2.4 Radiated Coupling in DSP Coupling generated by radiation is commonly known as crosstalk. Crosstalk is caused by the electromagnetic field generated when current flows through a conductor, which induces transient currents in nearby conductors. 2.5 Radiation Phenomena in DSP Radiation has two basic types: differential (DM) and common-mode (CM). Common-mode radiation or monopole antenna radiation is caused by unintentional voltage drops, which raise all ground connections in the circuit above the system ground potential. In terms of electric field magnitude, CM radiation is a more serious problem than DM radiation. To minimize CM radiation, the common-mode current must be reduced to zero by a practical design. 2.6 Factors affecting EMC (1) Voltage: The higher the power supply voltage, the greater the voltage amplitude and the more radiation, while a low power supply voltage affects sensitivity. (2) Frequency: High-frequency signals and periodic signals will generate more radiation. In high-frequency digital systems, current spikes will be generated when devices are in a switching state; in analog systems, current spikes will also be generated when the load current changes. (3) Grounding: In circuit design, nothing is more important than using a reliable and perfect ground connection. Most of the EMC problems are caused by improper grounding. There are three signal grounding methods: single-point, multi-point, and hybrid. When the frequency is below 1MHz, a single-point grounding method can be used; in high-frequency applications, it is best to use multi-point grounding; hybrid grounding is a combination of single-point grounding for low frequency and multi-point grounding for high frequency. However, the ground loops of high-frequency digital circuits and low-level analog circuits must never be mixed. (4) PCB design: Proper printed circuit board (PCB) routing is crucial to prevent electromagnetic interference. (5) Power supply decoupling: When devices are switched, transient currents are generated on the power lines. These transient currents must be attenuated and filtered out. Transient currents from high di/dt sources cause ground and trace “emit” voltages. High di/dt generates a wide range of high-frequency currents that excite components and cables to radiate. Changes in current and inductance flowing through the conductors cause voltage drops. Reducing the inductance or the change in current over time can minimize this voltage drop [2]. 2.7 Hardware noise reduction techniques for DSP 2.7.1 Noise reduction techniques in terms of board structure and circuit arrangement (1) Use ground and power planes; (2) The plane area should be large to provide low impedance for power decoupling; (3) Minimize surface conductors; (4) Use narrow lines (4 to 8 mils) to increase high-frequency damping and reduce capacitive coupling; (5) Separate digital, analog, receiver, and transmitter ground/power lines; (6) Separate circuits on the PCB according to frequency and type; (7) Do not cut the PCB, as traces near the cut may cause unwanted loops; (8) Using a stacked structure is the best preventive measure against most signal integrity and EMC problems. It can effectively control impedance, and its internal traces can form an easy-to-understand and predictable transmission line structure. (9) Seal the traces between the power supply and the ground plane; (10) Keep the spacing between adjacent excitation traces greater than the width of the traces to minimize crosstalk; (11) The loop area of ​​the clock signal should be as small as possible; (12) High-speed lines and clock signal lines should be short and directly connected; (13) Sensitive traces should not run parallel to traces that transmit high-current fast switching signals; (14) Avoid floating digital inputs to prevent unnecessary switching and noise generation; (15) Avoid power supply under crystal oscillators and other inherently noisy circuits. (15) The corresponding power, ground, signal and return traces should be arranged in parallel to eliminate noise; (16) Separate the clock line, bus and chip enable from the input/output lines and connectors; (17) Make the line clock signal orthogonal to the I/O signal; (18) To minimize crosstalk, the traces should be crossed at right angles and the ground line should be scattered; (19) Protect the critical traces (use 4 to 8 mil traces to minimize inductance, the traces should be close to the ground plane, the interlayer structure between the layers should be protected with ground on each side of the interlayer). 2.7.2 Noise Reduction Method Using Filtering Techniques (1) Filter the power lines and all signals entering the PCB, and decouple them at each pin of the IC using high-frequency low-inductance ceramic capacitors (0.1 mF for 14MHz and 0.01 mF for over 15MHz); (2) Bypass all power supply and reference voltage pins of the analog circuit; (3) Bypass fast switching devices; (4) Decouple the power supply/ground at the device leads; (5) Use multi-stage filtering to attenuate multi-band power supply noise; (6) Mount the crystal oscillator on the board and ground it; (7) Add shielding in appropriate places; (8) Arrange the adjacent ground lines close to the signal lines to more effectively prevent the emergence of new electric fields; (9) Place the decoupling line driver and receiver appropriately close to the actual I/O interface, which can reduce the coupling between the PCB and other circuits and reduce radiation and sensitivity; (10) Shield and twist the interfering leads together to eliminate mutual coupling on the PCB; (11) Add clamping diodes to inductive loads. 3 Measures to be taken in DSP software design Software interference mainly manifests in the following aspects: (1) Incorrect algorithms produce incorrect results. The main reason is that the program exponential operation in the computer processor is an approximate calculation, and the result sometimes has a large error, which is easy to cause malfunctions; (2) Due to the low precision of the computer, and the need to align the order when performing addition and subtraction operations, the large number "eats up" the small number, resulting in error accumulation and underflow, which is also one of the sources of noise; (3) Due to hardware interference, the computer may experience phenomena such as changes in the program counter PC value, increased data acquisition error, control failure, changes in RAM data due to interference, and "deadlock" in the system. 3.1 Methods for intercepting runaway programs (1) In program design, single-byte instructions should be used more often, and some no-operation instructions should be inserted at key points, or the effective single-byte instructions should be repeated several times. This can protect the subsequent instructions from being broken up and make the program run on the right track; (2) Add software traps: When the PC value is out of control and the program is out of control, the CPU enters the non-program area. At this time, a boot instruction can be used to force the program to enter the initial entry state and enter the program area. A trap can be set every certain period of time; (3) Software reset: When the program "runs away", the monitoring system is run to make the system automatically reset and re-initialize. 3.2 Set up a flag to judge Define a certain unit as a flag. In the main program of the module, set the value of the unit to a certain characteristic value. Then, at the end of the main program, judge whether the value of the unit remains unchanged. If it is different, it means there is an error, and the program will enter the error handling subroutine. 3.3 Add data security backup Important data should be stored in two or more storage areas. Large-capacity external RAM can also be used to back up the data. Permanent data is stored in a table in the EPROM, which can prevent the data and table from being damaged and ensure that the data is not used as instructions when the program logic is chaotic[3]. 4 Key factors to consider when designing with EDA tools The design of high-speed digital circuits requires both the experience of the designers and the support of excellent EDA tools. EDA software has become multifunctional and intelligent. With the application of high-density single-chip ball grid array packaging, high-density connectors, micro-via built-in technology and 3D boards in printed circuit board design, layout and routing have become increasingly integrated and have become an important part of the design process. Software technologies such as automatic layout and free-angle routing have gradually become important methods to solve such highly integrated problems. Using such software, manufacturable circuit boards can be designed within a specified time. At present, due to the increasingly shorter product launch time, manual routing is extremely time-consuming and can no longer meet the requirements. Therefore, it is now required that layout and routing tools have automatic routing functions to quickly respond to the higher requirements of the market for product design. 4.1 Automated Routing Technology Due to the need to consider electromagnetic compatibility (EMC), electromagnetic interference, crosstalk, signal delay, and high-density design factors such as differential pair routing, the constraints on placement and routing are increasing every year. A few years ago, a typical circuit board required only 6 differential pairs for routing, but now it requires 600 pairs. It is impossible to achieve these 600 pairs of routing manually within a certain timeframe, therefore automated routing tools are essential. Although the number of nets in today's designs has not changed significantly compared to a few years ago, only the complexity of the silicon wafer has increased, the proportion of critical nodes in the design has increased significantly. Of course, for some particularly critical nodes, placement and routing tools need to be able to distinguish them, but it is not necessary to restrict every pin or node. 4.2 Considerations for Using Free-Angle Routing Technology With the increase in integrated functions on monolithic devices, the number of output pins has also increased significantly, but the package size has not increased accordingly. Coupled with the limitations of pin spacing and impedance factors, these devices must use finer linewidths. At the same time, the overall reduction in product size means that the space available for placement and routing has also decreased significantly. In some DSP products, the size of the baseboard is almost the same as the size of the devices on it, and the components occupy up to 80% of the board area. Some high-density components have interlaced pins, and even with tools that have 45° routing capabilities, automatic routing is not possible. Free-angle routing tools, on the other hand, have great flexibility and can maximize the routing density; their pull-tight function allows each node to automatically shorten after routing to meet space requirements; they can greatly reduce signal delay and reduce the number of parallel paths, which helps to avoid crosstalk. Using free-angle routing technology can make the design manufacturable and the designed circuit has good performance. 4.3 Technologies to be used for high-density devices The latest high-density system-on-a-chip uses BGA or COB packaging, and the pin pitch is getting smaller and smaller, with the ball pitch as low as 1mm and continuing to decrease. This makes it impossible to use traditional routing tools to bring out the signal lines of the package. There are currently two ways to solve this problem: (1) bring out the signal lines from the lower layer through the holes under the ball; (2) use ultra-fine routing and free-angle routing to find a lead path in the ball grid array. For high-density devices, using wiring methods with extremely small widths and spaces is the only feasible approach, as this is the only way to guarantee a high yield. Modern wiring technology also requires the ability to automatically apply these constraints. Free routing methods can reduce the number of wiring layers and lower product costs. It also means that, without changing costs, more ground and power layers can be added to improve signal integrity and EMC performance. 4.4 The application of other new circuit board design and fabrication technologies, such as microvia plasma etching, in the multilayer board fabrication process of DSPs has greatly improved the performance of placement and routing tools. Adding a new via within the path width using plasma etching does not increase the cost of the substrate itself or manufacturing costs, because the cost of creating a thousand vias using plasma etching is as low as the cost of creating a single via. This requires routing tools to be more flexible, capable of applying different constraints and adapting to different microvia and fabrication techniques. The increasing component density also impacts placement design. Placement and routing tools always assume that there is sufficient space on the board for component release mechanisms to release surfaces for new components without affecting existing components. However, sequential component placement presents a problem: the optimal position of each component on the board changes every time a new component is placed. This explains the low level of automation and high degree of manual intervention in the placement design process. Although current placement tools have little limit on the number of components that can be placed sequentially, some engineers believe that placement tools are actually limited when used for sequential placement, with a limit of approximately 500 components. Others believe that placing up to 4000 components on a single board can cause significant problems. Compared to sequential algorithms, parallel placement techniques achieve better automated placement results. 4.5 3D Placement Tools 3D tools are primarily used for the placement and routing of increasingly widely used irregular and standard-shaped boards. For example, Zuken's latest Freedom tool first uses a 3D baseboard model for spatial component placement, then performs 2D routing. The routing process can also indicate whether the board is manufacturable. Routing tools must also be able to handle designs using shaded difference pairs on two different layers, as this design method has become increasingly important. As signal frequencies continue to increase, tools that integrate layout and routing tools with advanced simulation tools for virtual prototyping have emerged, such as Zuken's nbspHot Stage tool. Therefore, routing issues can be considered even in the virtual prototyping stage. We believe that new software technologies such as free-angle routing, automatic layout, and 3D layout will become common design tools for board designers, just like automatic routing technology. Designers can use these new tools to solve new technical problems such as electromagnetic compatibility in microvia and monolithic high-density integrated systems [4]. 5 Conclusion Electromagnetic compatibility technology involves a wide frequency range of 0 to 400 GHz. In addition to traditional facilities, the research objects involve electromagnetic environments ranging from the chip level to various types of ships, space shuttles, intercontinental missiles, and even the entire Earth. Electromagnetic compatibility technology is also an important issue to be considered in DSP system design. Appropriate noise reduction technology should be adopted to make the DSP system conform to EMC standards. Its electromagnetic compatibility is a key research area with distinctive characteristics. Many countries have not only strengthened their own research in this area, but also established international organizations to facilitate communication and standardization. With my country's accession to the WTO, products that fail to meet international standards in electromagnetic compatibility (EMC) will lack competitiveness, be unable to penetrate the international market, and have no market domestically. Therefore, in the 21st century, resolving EMC issues in electrical and electronic products (including DSP systems) and effectively improving product quality to make them "green products" is of paramount importance.