Abstract: This paper introduces the architecture design and general OEM hardware selection of a new generation of embedded telemetry front-end processor based on the cPCI bus, focuses on the design and implementation of a multi-functional dual-channel PCM splitter board, and briefly describes the software in the telemetry front-end processor.
Keywords: Embedded telemetry front-end processor, cPCI bus splitter
Telemetry data processing systems have wide applications in military testing fields such as aviation and aerospace. In aviation flight testing, these systems provide the means and platform for real-time processing of various flight test data. They are essential facilities for test pilots, flight commanders, and flight engineers to collaboratively complete new aircraft flight tests, and are crucial for ensuring modern aircraft flight safety, improving flight test efficiency, shortening flight test cycles, and achieving comprehensive flight testing. The core equipment in the telemetry data processing system—the telemetry front-end processor—has undergone rapid technological development from discrete and intelligent to embedded systems. my country's research and development of telemetry front-end processors has progressed from importation and collaborative development to complete independent development. The telemetry front-end processor is an embedded real-time computer system that undertakes real-time processing tasks such as synchronization, splitting, engineering unit conversion, data calculation, and data distribution of telemetry PCM data. It is connected and integrated with telemetry system management servers, workstations, and other devices through network connections to form the currently popular C/S-based telemetry data processing system. It can be said that the technological level of the telemetry front-end processor represents the technological level of the telemetry data processing system.
1. System Functions and Main Technical Specifications
In simple terms, the function of a telemetry front-end processor is to synchronize, split, merge, and store multiple serial PCM (Pulse Code Modulation) data streams from telemetry receiving equipment. It then performs real-time processing on the converted parallel data, including engineering unit conversion and parameter calculation, before transmitting the data to a display workstation via a network. Furthermore, by replaying the telemetry recorded data, it provides users with the same processing capabilities as real-time methods, but with more detailed data analysis functions. The main technical specifications of the telemetry front-end processor are:
(1) It can simultaneously synchronize and split two PCM data streams, with each PCM stream having a rate of no more than 20Mbps.
(2) Real-time data processing rate: 20Mbps.
(3) Data transmission: switched Ethernet, network bandwidth 1000Mbps, broadcast mode and "point-to-point" mode.
(4) Data storage: The data storage shall be maintained at the maximum speed without loss, and the disk capacity shall be sufficient for a recording time of not less than 4 hours.
(5) D/A output: 12-bit, 16-channel analog signal output.
2 System Composition and Architecture Design
In the 1990s, due to limitations in computer technology at the time, most embedded telemetry front-end processors, both domestically and internationally, adopted a computer platform based on the VME bus and an architecture with dual buses, multiple CPUs, and 100Mbps Ethernet interfaces. This architecture was technically complex, costly, difficult to develop software, and had a long system development cycle. Current advancements in computer technology have rendered CPU speed and bus speed no longer bottlenecks for next-generation embedded telemetry front-end processors. An architecture based on a single CPU, single bus, and gigabit Ethernet interface has become the mainstream design for next-generation embedded telemetry front-end processors. The modularized telemetry front-end devices, such as code synchronizers, splitters, and time code generators, are embedded into industrial computer systems as plug-in boards. Their composition has been simplified to: a 19-inch computer chassis, a CPU board, a multi-functional PCM splitter board, a time code board, a D/A board, and storage devices. A typical structure and composition are shown in Figure 1. The new generation of embedded telemetry front-end processors features a simplified architecture, improved performance and reliability, reduced cost, shorter development cycles, and easier integration into multi-datastream telemetry data processing systems based on a client/server architecture.
3 Hardware Design
3.1 Selection of Bus Platform and OEM Board
The computer bus platform is crucial for embedded telemetry front-end processors. Currently, most foreign embedded telemetry front-end processors utilize the popular Compact PCI computer bus platform. This platform incorporates the latest advancements in commercial PC technology, and its data transmission rate meets the requirements of next-generation embedded telemetry front-end processors handling multiple PCM data streams in real time. Its environmental conditions and reliability also meet the requirements for use in transport aircraft and ground-based vehicle environments. All other hardware in the telemetry front-end processor, except for the PCM splitter board, are OEM products. The chassis is a 12-slot Compact PCI chassis (including power supply and hard disk). Based on the processing requirements, the CPU board in this design is a C7 series from SBS (USA), with a CPU PⅢ 1GHz, 1GB RAM, two 1000Mb Ethernet ports, and one SCSI port. The timecode board is a BC637 from Datam (USA) with GPS timing; the D/A board is an N16713 series from National Instruments (USA), with 8 channels per board, 1MSps per channel, and a 12-bit D/A resolution. Considering that monolithic all-digital code synchronizers are already in use abroad, a chip space for a monolithic code synchronizer has been reserved in the design of the multi-functional dual PCM splitter board. This design uses an external code synchronizer.
3.2 Design and Implementation of Multifunctional Dual PCM Splitter Board
The PCM splitter board is a key component of the embedded telemetry front-end processor. While there are many OEM products available overseas that offer single-board, single-PCM splitter options, the acquisition of high-end products is subject to numerous restrictions imposed by Western countries. Therefore, we opted for a self-designed technical approach and successfully developed a multi-functional dual-channel PCM splitter board based on the Compact PCI bus. Its technical level has reached the current international advanced level.
3.2.1 Hardware Logic Design of PCM Splitter Board
The block diagram of the multifunctional dual PCM splitter is shown in Figure 2. It consists of a dual PCM splitter (including frame synchronization detection, frame/subframe synchronization strategy and corresponding timing control logic, etc.), a PCM simulator, voice acquisition and other functional modules. The main functions are all implemented by large-scale integrated circuit CPLD programmable logic chips.
The CPLD uses the Latfice ISP 4512V system-in-the-loop programmable device. The ISP's ease of field modification reduces development costs and shortens system debugging time. Among many common PCI interface chips, the mainstream chip currently used in industry designs, the PLX9054 from PLX Corporation, was selected. The PLX9054 is a powerful, flexible, 32-bit, 33MHz PCI bus interface controller that conforms to the PCI IV 2.2 specification. It can act as a master device to control the PCI bus or as a target device to respond to the bus. The PLX9054 provides three interfaces: PCI bus, EWROM, and IDCAL bus. As a "bridge" chip, it offers three direct data transfer modes between the PCI bus and the IDCAL bus. This design uses the DMA data transfer mode. With its powerful functionality and simple user interface, the PLX9054 provides a concise method for PCI bus interface development. Designers only need to design the local bus interface control circuit to achieve high-speed data transfer with the PCI bus.
3.2.2 Frame and subframe synchronization and implementation of synchronization strategies
PCM data parameters are expressed as one or more words, each word consisting of several code elements. In a PCM acquisition system, all test parameters form a parameter group, called the frame/subframe structure. Accurately distinguishing the start position of each word and correctly recovering the parallel data of the acquired parameters—that is, acquiring a pulse sequence whose start time matches the frame/subframe and the data words representing each parameter—is called frame/subframe synchronization. The role of the frame/subframe synchronization signal is to provide a start time marker within a signal group, enabling correct splitting of each parameter word. Its characteristics are: it has a small information content but requires high transmission reliability. The frame synchronization detector is a crucial component of the PCM splitter board; all other operations are performed after the frame synchronization detector completes correct detection. Therefore, the frame synchronization detector plays a vital role. Its block diagram is shown in Figure 3.
According to the format requirements of the data acquisition scheme, the processor is pre-initialized, including the frame synchronization code group, the length of the synchronization code group, and the allowed number of error bits for the synchronization code group. As time progresses, PCM data, under the control of the CLDCK signal, enters the shift register bit by bit. The output data of the shift register enters the comparator, which compares it with the frame synchronization code group at any time. Under the control of the synchronization code group length logic, once a possible synchronization code group is detected, the comparator outputs a synchronization signal. This synchronization signal must be decided by a decision unit to determine its validity. The method is to pre-set the allowed error tolerance, i.e., the allowed number of error bits, and then determine the output of the true synchronization signal based on whether the comparator's output signal meets the error tolerance requirements. The generation of the frame synchronization signal provides the most basic and important timing basis for the entire PCM splitter board. The frame synchronization strategy is one of the key technologies of PCM splitting. Its significance lies in minimizing the "missed synchronization" and "false synchronization" phenomena caused during data transmission, thereby reducing the bit error rate and further improving the reliability and effectiveness of data detection. A basic and proven effective frame synchronization strategy is as follows: after frame synchronization detection is completed, according to the PCM word length and frame length defined in the PCM format, if several (usually three) matching synchronization code groups are found consecutively, the frame is considered to be synchronized. The logical implementation of the frame synchronization strategy is shown in Figure 4. As can be seen from Figure 4, the correctness of frame synchronization can be based on the following conditions:
(1) The correctness of the synchronization code group.
(2) Frame length correctness (achieved by comparing the frame length counter with the frame length preset value).
(3) Synchronization, detection, and out-of-synchronization judgment. Different designers may use different methods to eliminate the effects of false synchronization and missed synchronization. The following methods can be adopted: if the comparator has three consecutive equal values, it will synchronize; if there is one unequal value, it will enter the detection state; and if it has three consecutive unequal values or fails to synchronize after a certain period of detection, it will enter the out-of-synchronization state.
The above solves the frame synchronization problem, that is, it finds the start and end positions of each frame. However, the data words of each frame cannot be the same in a specific test scheme. How to determine which position of a certain parameter word is in which frame? After frame synchronization, is the correct position of data transmission reliable? This is the problem that subframe synchronization needs to solve. For many years, the ID synchronization method has been widely used for frame synchronization both domestically and internationally. Subframe synchronization strategy is another key technology of PCM splitting. Its significance lies in: on the basis of frame synchronization, to perform further fault-tolerant detection on the reliability of data. A commonly used and relatively reliable subframe synchronization strategy is: continuously check the data of several subframes (usually 3). If the ID words at the same position in the subframe are the same or the corresponding ID words of adjacent subframes are consecutive, then the subframe is determined to be synchronized; otherwise, the subframe is not synchronized. The logic implementation of the subframe synchronization strategy is shown in Figure 5. As can be seen from Figure 5, the correctness of subframe synchronization and strategy depends on the following conditions:
(1) The correctness of the ID word position and its value (such as zero crossing detection).
(2) Correctness of subframe length (judged by comparing subframe length with frame counter value).
(3) The methods for determining synchronization, detection, and loss of synchronization are similar to those for frame synchronization strategies.
In this design, dual PCM frame synchronization detection and frame/subframe synchronization strategies are implemented using CPLD logic devices, which not only improves the integration of the design but also enhances the reliability and performance of the system, enabling each PCM branch rate to reach the internationally advanced level of 20Mbps.
4. Software Platform Selection and Software Components
Currently, the commonly used operating systems for telemetry front-end processors are Windows 2000 and VxWorks. Windows 2000 is universal, has abundant software resources, is easy to use and expand; while VxWorks is a widely used real-time operating system with good real-time performance, reliability and scalability. Based on the actual needs of telemetry data processing, this design chose Windows 2000, and the programming language was C++. The software composition of the telemetry front-end processor and the flowchart of real-time data processing are shown in Figure 6.
Figure 6. Telemetry front-end processor software composition and actual wage data processing flow.The software in the telemetry front-end processor consists of modules for PCM data acquisition, parameter extraction, engineering unit conversion, data merging and parameter calculation, alarm parameter processing, data storage, network communication, and data distribution. The acquisition, parameter extraction, and engineering unit conversion modules correspond to data streams, with each data stream having its own separate module. After PCM data is acquired, parameters are extracted, engineering units are converted, and necessary processing and storage are performed according to predefined parameters. Data requiring simulated output is directly output from the D/A board according to pre-set parameters. Engineering unit data and raw data are transmitted to the workstation via the network, where the workstation performs various visualization displays of the telemetry data and provides dedicated data analysis and processing for flight tests. The design and implementation of a new generation of embedded telemetry front-end processor based on the cPCI bus makes the integration of telemetry data processing systems easier. Its 20Mbps rate, dual-channel PCM data splitting, and real-time processing capabilities meet the telemetry data processing requirements of modern military and civil aircraft flight tests. Its application has greatly improved my country's flight test telemetry data processing technology. Meanwhile, the ruggedized features of the cPCI bus enable real-time telemetry data processing systems, which are based on embedded telemetry front-end processors, to meet the requirements of airborne transport aircraft and ground vehicle environments. This broadens the application scope of telemetry front-end processors in military and civilian industrial testing, and has broad application prospects.
