Abstract: This paper first introduces the working principle of the PCI9052 PCI bus controller and the SJA1000 CAN bus communication controller, and then introduces the hardware and software implementation methods of the PCI bus and CAN bus communication controller interface. Keywords: PCI bus; CAN bus; communication controller Introduction Distributed industrial measurement and control systems require fieldbuses to connect various field devices and processing control units. The CAN bus is a fieldbus with a high performance-price ratio that can meet the requirements of distributed control and has broad application prospects. It is actually a simplified network structure, extremely useful in constructing single-chip processor networks. To enable the host computer to connect to the CAN bus, making the microcomputer the host computer of the system, enhancing the functions of the control system, and further extending the CAN bus connectivity range, an interface between the microcomputer and the CAN bus is needed. This paper introduces a CAN bus PCI adapter designed and manufactured by the author. Hardware Design of the Interface Implementation of the PCI Interface Currently, there are some CAN bus adapters on the market, but most are based on PC/104 or ISA buses, resulting in slow transmission speeds and low efficiency. The author uses the high-efficiency PCI bus in the design to achieve high-speed data transmission. Compared to the ISA bus, the PCI bus has the following characteristics: ① High transmission speed. The PCI bus is 32-bit wide (expandable to 64-bit). The clock frequency is 0-33MHz. It supports burst transfers, and the transmission speed can reach 132Mb/s. In comparison, the ISA bus is 8/16-bit wide, with a clock frequency of 8MHz, does not support burst transfers, and has a transmission rate of only 8Mb/s; ② Plug and play. PCI achieves true plug and play. The system can automatically configure PCI devices; ③ Long lifespan. The PCI bus is processor-independent (through a bridge or direct integration), and can support various series of processors, including future next-generation processors. Due to the complexity of the PCI bus specification, its interface design is difficult, but many manufacturers currently provide dedicated PCI interface chips. Most of these interface chips are fully compatible with PCI bus specification versions 2.1 and 2.2, thus greatly reducing the workload of PCI board design. PCI devices can be divided into master mode and slave mode. The master mode can perform DMA operations, while the slave mode can only perform read and write operations. Based on the data transmission bandwidth provided by PCI (maximum 132Mb/s) and the requirements of the CAN bus (maximum 1Mbps), coupled with economic considerations and the challenges and timelines of development (master mode bridge chips are more expensive and more difficult to develop), and since DMA functionality is not required, a slave mode bridge chip is sufficient to meet the data transmission needs. Furthermore, chip selection must consider not only performance and economic requirements but also the ease of hardware and driver development. Without sufficient chip specifications, application examples, and development tools, development difficulty will be significantly increased and the development cycle extended. Here, we use PLX's PCI9052 PCI bus target interface chip as the PCI bus interface chip for the CAN bus adapter, responsible for data communication with the computer. The 9052 is a low-cost PCI bus slave mode interface chip developed by PLX, with low power consumption, conforming to the PCI 2.1 specification, and providing a local bus that can be programmed to be an 8/16/32-bit (non-)multiplexed bus. The implementation of the CAN bus interface: The reason why the CAN bus has maintained rapid development both domestically and globally is entirely due to its superior performance. The CAN bus is primarily used in the automotive industry. With advancements in integrated circuit technology and cost reductions, it has gained increasing acceptance among software and hardware engineers in the control field, and is widely used in control networks across various industries. Its main performance indicators are as follows: ① Multi-station arbitration structure (address priority, non-destructive arbitration); ② Support for master-slave broadcast mode; ③ Up to 110 nodes without any expansion; ④ Maximum communication rate of 1Mbps, maximum communication distance of 5km; ⑤ Typically, the CAN controller has internal receive and transmit buffers; ⑥ Communication is in frames, with a maximum of 8 bytes of data; ⑦ Automatic 16-bit CRC checksum; ⑧ Strong bus and communication error management capabilities. Since the PCI9052 can initiate local bus read/write operations, the CAN card no longer requires a microcontroller; a CAN communication controller is sufficient. This card uses the SJA1000. The SJA1000 supports both basic AN (BisicCAN) and enhanced CAN (PeliCAN) operating modes, and supports the CAN 2.0B protocol specification with new features. Featuring FIFO and hot-swappable functionality, this chip not only implements CAN bus interface functions but also outputs a programmable signal CLKOUT based on the crystal oscillator frequency. This signal can be used as the bus frequency for the PCI9052 local bus, saving components and simplifying the design. The CAN bus frequency can be 12MHz, 6MHz, or 24MHz, and the PCI9052 automatically synchronizes access between the local bus and the PCI bus. The CAN bus transceiver uses the 82C250. This chip serves as the interface between the CAN bus controller and the physical bus, providing differential transmission and reception capabilities for the CAN bus. It has the ability to resist transient interference and protect the bus, and RF interference can be reduced by adjusting the edge slope of the communication pulses on the CAN bus. Its speed can reach 1Mbps, and the maximum number of nodes can reach 110. Address decoding and logic control are performed by the EPM7064S. The EPM7064S is a type of the ALTERA MAX7000 series. It mainly implements address decoding for two independent CAN bus channels and drives and levels the control signals. The EPM7064S improves system reliability, reduces board size, and facilitates future expansion of board functionality. To enable reinitialization in case of CAN bus channel failure, two MAX811 reset chips are used in the interface card. The EPM7064S generates control signals to reset the SJA1000 controller when a CAN bus channel malfunctions. Its bus interface schematic is shown in Figure 1. PCI provides a configuration space for each PCI device to achieve plug-and-play (PnP). During PC power-on self-test, the configuration software scans the PCI bus, detects all PCI devices, reads configuration information, and allocates system resources to each PCI device, enabling PnP. Each PCI functional device has a 64-double-word configuration space, storing the functions supported by the device in a specific format. The PCI protocol defines the format and purpose of the first 16 double words, called the device's configuration header area. The other 48 double words are device-specific. The CAN card's hardware resources consist of a memory-mapped space mapping the SJA1000's internal registers and an interrupt source. The PCI9052 provides five local address spaces, one of which can be selected as the address space for the SJA1000, allocating 32 8-bit address spaces. Simultaneously, corresponding initialization is configured: the PCIBAR2 register in the PCI configuration register is set to 0xFFFFFFE0, requesting memory allocation of 32 bytes from the system, with the type being non-readable; other register values ​​can be set to 0. The range of the local address space is set to 0x00000000～0x00000020. Interrupt configuration involves assigning the PCI interrupt request line to a specific ISA interrupt request (IRQ) line in the system. This control card uses a serial EEPROM (93C46B) to store the PCI configuration information. After power-on, the 93C46B is accessed to achieve automatic configuration of the control card. [IMG=Bus Interface Schematic]/uploadpic/THESIS/2007/12/20071224152214259669.jpg[/IMG] Figure 1 Bus Interface Schematic Interface Software Design The software design includes the design of the PCI driver and the COM component. Since the interrupts, I/O ports, mapped memory, and other resources of the PCI device are dynamically allocated, a driver program must be written to manage the hardware for user programming. The CAN card driver development tool uses WINDRIVER. Because the CAN card does not have a microcontroller, all operations on the bus port are performed by the driver program. This not only allows the computer to implement complex functions, such as error detection and breakpoint resumption, but also saves hardware and facilitates card upgrades—only the driver needs to be replaced. The driver program's main functions are configuring the SJA1000 interface, transmitting and receiving data on the CAN bus, real-time monitoring of the bus, and receiving transmit and receive commands from the user program. Both data transmission and reception and CAN bus errors are handled via interrupts, allowing the driver to respond quickly and directly notify the user program through the Event kernel object. The initialization of the CAN bus communication adapter is a crucial and challenging aspect of CAN bus design. Parameters that need to be set during initialization include clock, bus configuration, flag identifier mask segment, extended identifier mask segment, information block, timer 0, timer 1, information block control segment, and information block operating mode. A simplified flowchart of the CAN bus adapter is shown in Figure 2. [IMG=Simplified Flowchart of CAN Bus Adapter]/uploadpic/THESIS/2007/12/2007122415222358821H.jpg[/IMG] Figure 2 Simplified Flowchart of CAN Bus Adapter Conclusion The CAN bus adapter designed in this paper has a simple structure and can be used in distributed fieldbus control systems. After long-term testing under WIN2000, it has proven to be stable and reliable. It can adapt to different transmission rates and distances, effectively ensuring the real-time performance of industrial process monitoring while reducing the workload of the host computer and meeting diverse user requirements. The IV characteristics of SNTSCRs for chip ESD protection under different gate bias and distributed parameter conditions have been described in detail in CMOS processes. The ability of SNTSCRs to maintain high ESD levels over small areas is attractive in modern high-integration science. Without using thick gate oxide layers, typically less than 0.25μm in CMOS processes, SNTSCRs are fully compatible in effectively protecting mixed-voltage interface circuits from ESD damage.