Beijing, China, September 29, 2021 - Tektronix, a leading global provider of test and measurement solutions, today released KTE V7.1 software for Keithley S530 Series Parametric Test Systems, helping to accelerate semiconductor chip manufacturing processes at a time when they are most needed in the global market.
New options introduced for the first time in KTE V7.1 include a new parallel testing function and a unique high-voltage capacitor testing option, suitable for emerging power and wide-bandgap applications. Compared to KTE V5.8, KTE V7.1 reduces test time by more than 10%, meaning engineers can reduce downtime and manufacture chips faster.
The rise of 5G and the development of the Internet of Things have driven global demand for semiconductors. The global shortage not only necessitates increased manufacturing capabilities but also the ability to test new chips under development more quickly. Tektronix's new testing system helps accelerate manufacturing by reducing testing time, thereby speeding up the time-to-market for new chips.
“Today’s emerging analog, wide-bandgap (SiC and GaN) and power semiconductor technologies require parameter testing to maximize measurement performance, accommodate a broad product portfolio, and minimize costs,” said Peter Griffiths, General Manager of Systems and Software at Tektronix. “Our customers, including the world’s largest chipmakers, will benefit from the enhancements of KTE V7.1, enabling engineers to continuously design innovative solutions at an unprecedented pace to meet evolving market demands.”
The release of KTE V7.1 builds upon KTE 7.0, improving the functionality and throughput of the S530 system. A new test head design allows for flexible use of different probe plug-ins. Upgraded software and hardware enable one-pass testing and high throughput. In terms of service, the newly released System Reference Unit (SRU) reduces calibration time to under 8 hours, meaning calibration can be completed within a regular work shift. SRUs can be purchased directly or through an annual SSO service plan.
Significant advancements and industry firsts
1) Parallel testing capabilities further improve production efficiency and reduce testing costs.
First offered as an option in KTE V7.1, the S530 now boasts powerful parallel testing options for further improvements in productivity and reduced testing costs, with an expected improvement range of up to 30% (depending on the test and architecture). Keithley's parallel test software is built on the S530's unique hardware architecture, supporting up to eight high-resolution SMUs that can be connected to any test pin via any full Kelvin port/row in the system, optimizing the efficiency of all system resources to maximize test throughput.
2) Provides unique high-voltage capacitor testing capabilities for emerging power supplies and wide-bandgap applications.
Today's engineers need to test high-voltage equipment, and the demand for chips with faster switching speeds and higher switching efficiency is constantly growing. Higher efficiency means less power consumption and less heat generation, which is also beneficial to our environment. To test wide-bandgap devices operating at higher voltages, engineers are moving from R&D labs to manufacturing. A unique feature in KTE V7.1 is its dedicated High Voltage Capacitor Voltage (HVCV) option, which can be used in conjunction with the industry's only single-pass test solution to measure voltages from 200 to 1000 V, enabling testing of DC bias capacitors up to 1100 V. This production-ready feature allows for precise measurement of Cdg, Cgs, and Cds, supporting the characterization and testing of the input and output transient performance of power devices.
3) Test up to 1100 V on any pin using a single probe grounding.
In addition to providing and measuring voltages up to 1100 V, a single S530-HV system can be configured with up to two 2470 SMUs. Through the high-voltage switching matrix within the S530-HV, users can perform these measurements at any time on any test pin. This achieves maximum flexibility, accommodating pin output requirements for a wide variety of test device and architecture combinations, eliminating the throughput latency and higher costs associated with double-testing or dedicated pin methods.
