I. Background of Evolution in Embedded System Design Methodologies The evolution of embedded system design methodologies is generally driven by application demands and the advancement of IT technology. With continuous innovation and development in microelectronics technology, the integration level and process technology of large-scale integrated circuits have been continuously improving. The combination of silicon materials and human ingenuity has led to the production of large quantities of low-cost, high-reliability, and high-precision microelectronic structural modules, propelling the development of a completely new technological field and industry. Based on this, the concept of programmable devices and microprocessor technology have enabled software to modify and implement hardware functions. The widespread application of microprocessors and various programmable large-scale integrated circuits and semi-custom devices has opened up a new world of applications, profoundly influencing and gradually changing human social activities such as production, life, and learning. The significant improvement in the performance of computer hardware platforms has enabled the implementation of many complex algorithms and user-friendly interfaces, greatly improving work efficiency and providing a physical basis for the computer-aided design of complex embedded systems. High-performance EDA synthesis development tools (platforms) have seen significant development, with continuously improving automation and intelligence. These tools provide easy-to-learn and convenient integrated development environments for complex embedded system design, offering various functions and levels including editing, placement, routing, compilation, synthesis, simulation, testing, verification, and device programming. The development of Hardware Description Languages ​​(HDLs) has provided a working medium for building various hardware models in complex electronic system design. Their strong descriptive and abstractive capabilities have brought about significant changes to hardware circuits, especially semi-custom large-scale integrated circuit design. Currently, widely used HDLs include VHDL (IEEE STD 1076 standard), Verilog HDL (IEEE STD 1364 standard), and Altera's AHDL (company standard). Due to the development and standardization of HDLs, a number of companies worldwide have emerged that specialize in designing various integrated circuit functional modules using HDLs. Their task is to describe the functions and structures of integrated circuits using HDLs according to common or special functions, and to create IP core modules at different levels of verification for chip designers to assemble or integrate. An IP (Intellectual Property) core module is a pre-designed, or even verified, integrated circuit, device, or component with a specific function. It comes in several different forms. IP core modules have three levels of design: behavioral, structural, and physical. These correspond to three layers: "soft IP core," which primarily describes the functional behavior; "firm IP core," which completes the structural description; and "hard IP core," which is based on the physical description and has undergone process verification. This is equivalent to the design technology of integrated circuits (devices or components) blanks, semi-finished products, and finished products. Soft IP cores are usually submitted to users using some kind of HDL text. They have undergone behavioral-level design optimization and functional verification, but do not contain any specific physical information. Based on this, users can synthesize the correct gate-level netlist and perform subsequent structural design, offering maximum flexibility. They can be easily integrated with other external logic circuits using EDA synthesis tools, and designed into devices with different performance characteristics according to various semiconductor processes. Commercially available soft IP cores generally have a total gate count of over 5000. However, improper subsequent design can lead to the failure of the entire result. Soft IP cores are also known as virtual devices. Hard IP cores are physical designs based on a specific semiconductor process, with a fixed topology and specific process, and have been verified by the process, guaranteeing performance. They are provided to users in the form of a circuit physical structure mask layout and a complete set of process documents, offering a ready-to-use complete technology. Solid IP cores have a design depth between soft and hard IP cores. In addition to completing all the design aspects of a hard IP core, they also complete gate-level synthesis and timing simulation. They are generally submitted to users in the form of a gate-level netlist. Manufacturers such as TI, Philips, and Atmel, through Intel licensing, use Intel's MCS51 IP core modules combined with their own strengths to develop customized microcontrollers compatible with Intel MCS51. Commonly used IP kernel modules include various CPUs (32/64-bit CISC/RISC CPUs or 8/16-bit microcontrollers/microcontrollers, such as the 8051), 32/64-bit DSPs (such as the 320C30), DRAM, SRAM, EEPROM, Flash memory, A/D, D/A converters, MPEG/JPEG, USB, PCI, standard interfaces, network units, compilers, encoders/decoders, and analog device modules. This rich IP kernel module library provides a fundamental guarantee for the rapid design of application-specific integrated circuits and single-chip systems, and for quickly capturing market share. Advances in software technology, especially the introduction of the Embedded Operating System (EOS), have provided underlying support and a high-efficiency development platform for developing complex embedded system application software. EOS is a powerful and widely used real-time multitasking system software. It generally possesses various system resource management functions found in operating systems, and users can implement various resource management functions through application programming interfaces (APIs). User programs can be developed and run on top of EOS. Compared to general-purpose operating systems (OS), embedded systems (EOS) are characterized by a smaller, more efficient kernel, lower overhead, stronger real-time performance, and higher reliability. A comprehensive EOS also provides drivers for various devices. To adapt to network and Internet applications, it can also provide TCP/IP protocol support. Currently popular EOS systems include 3Com's Palm OS, Microsoft's Windows CE and Windows NT Embedded 4.0, the University of Tokyo's Tron, various open-source embedded Linux distributions, and domestically developed systems such as Hopen OS from the Kaisi Group and HBOS from Zhejiang University. II. Changes in Embedded System Design Methods In the past, programmers skilled in software design generally avoided hardware circuit design, considering it a completely different field. With the development of electronic information technology, designers with electronic engineering backgrounds have gradually ventured into software programming. This primarily takes the form of learning assembly language programming through the application of microcontrollers (commonly known as single-chip microcomputers in China). When designing larger-scale distributed control systems, the ubiquitous PC is inevitably used as the upper-level machine. This allows for further learning of high-level languages ​​such as Quick BASIC, C, C++, VC, and VB to program the system, design the system interface, and establish a centralized distributed control system through multi-machine communication with a microcontroller-controlled front-end. Designers with a software programming background rarely have the interest to learn application circuit design. However, with the rapid development of computer technology, especially the invention of Hardware Description Language (HDL), system hardware design methods have changed. The hardware components and behavior of digital systems can be fully described and simulated using HDL. In this context, designing hardware circuits is no longer the sole domain of hardware design engineers. Designers skilled in software programming can use HDL tools to describe the behavior, function, structure, data flow, signal connections, and timing relationships of hardware circuits, designing hardware systems that meet various requirements. EDA tools allow for two design input methods, catering to the needs of hardware circuit designers and software programmers respectively. Hardware-background designers can use their familiar schematic input method, while software-background designers can use the hardware description language input method. Because HDL (Highly Descriptive Language) is used for input, it more closely resembles the description of system behavior and is easier to synthesize, transfer in the time domain, and modify. It also allows for the creation of process-independent design documents. Therefore, engineers skilled in software programming, once they master HDL and some necessary hardware knowledge, can often design better hardware circuits and systems than engineers accustomed to traditional design methods. Therefore, engineers accustomed to traditional design should learn to use HDL for description and programming. III. Three Levels of Embedded System Design Embedded system design has three different levels: 1. Level 1: Design method using PCB CAD software and ICE (Instrumentation Equipment) as the main tools. This is the method that has been used by microcontroller application system designers in China from the past to the present. Its steps are from abstraction to concretization. Abstract design mainly involves refining the system functions according to the functional requirements of the embedded application system, dividing them into several functional modules, drawing the system functional block diagram, and then allocating the hardware and software functions of the functional modules. Concrete design includes hardware design and software design. Hardware design mainly involves selecting and combining the components required for each functional module according to performance parameter requirements. The basic principle of selection is to choose the most cost-effective general-purpose components available on the market. When necessary, each uncertain part must be tested, its functionality verified, and its performance tested separately to find a relatively optimized solution from module to system, and to draw the circuit schematic. A key step in hardware design is to use PCB computer-aided design (CAD) software to lay out and route the system components, followed by PCB fabrication, assembly, and hardware debugging. The most labor-intensive part is software design. Software design runs through the entire system design process and mainly includes task analysis, resource allocation, module division, process design and refinement, coding and debugging, etc. The workload of software design is mainly concentrated in program debugging, so software debugging tools are key. The most commonly used and most effective tool is an in-circuit simulator (ICE). 2. Level 2: Design method based on EDA tools and EOS as development platform. With the development of microelectronics technology, various general-purpose programmable semi-custom logic devices have emerged. In hardware design, designers can use these semi-custom devices to gradually build application-specific integrated circuits (ASICs) from several standard logic devices that were originally interconnected through PCB circuits. In this way, the complexity of PCB layout and routing is transformed into the complexity of configuration within semi-custom devices. However, designing semi-custom devices does not require designers to have knowledge and experience in semiconductor processes and on-chip integrated circuit placement and routing. As semi-custom devices become larger and more integrated, the costs of interconnecting devices on the printed circuit board (PCB) decrease, reducing the cost of wiring, assembly, and debugging. This significantly reduces PCB area and the number of connectors, lowers overall system costs, increases the flexibility of programmable applications, and, more importantly, reduces system power consumption, increases system speed, and greatly improves system reliability and security. As a result, hardware designers have gradually shifted from selecting and using standard general-purpose integrated circuit devices to designing and fabricating some dedicated integrated circuit devices, supported by various EDA tools. Semi-custom logic devices have evolved from programmable logic arrays (PLAs) to programmable array logic (PALs), general-purpose array logic (GALs), complex programmable logic devices (CPLDs), and field-programmable gate arrays (FPGAs). The trend is towards increasing integration and speed, enhanced functionality, more rational structure, and greater flexibility and convenience. Designers can utilize various EDA tools and standard CPLDs and FPGAs to design and fabricate user-specific large-scale integrated circuits. Then, using a bottom-up design approach, the self-designed integrated circuits, programmable peripheral devices, selected ASICs, and embedded microprocessors or microcontrollers designed with semi-custom devices are laid out and wired on a printed circuit board to form a system. 3. The third level: a design method based on IP kernel libraries, using hardware-software co-design techniques. After the 1990s, there was a further shift from "integrated circuit" level design to "integrated system" level design. Currently, it has entered the single-chip system (SOC) design stage and is beginning to enter the practical application stage. This design method does not simply integrate all the integrated circuits needed by the system onto a single chip. If a single-chip system were implemented in this way, it would be impossible to achieve the high density, high speed, high performance, small size, low voltage, and low power consumption requirements of a single-chip system, especially the low power consumption requirement. Single-chip system design starts from the overall system performance requirements, closely integrating the design of microprocessors, model algorithms, chip structures, peripheral devices, and even the devices themselves. Through the co-design of system software and hardware based on a completely new concept, the entire system function is completed on a single chip. Sometimes, the system may be implemented on several chips. Because, in reality, not all systems can be implemented on a single chip; and the manufacturing cost of implementing a certain monolithic system may be too high, rendering it commercially unviable. Currently, the monolithic systems in practical use are still relatively simple, such as smart IC cards. However, several well-known semiconductor manufacturers are working intensively on the research and development of complex monolithic systems like single-chip PCs. Designing a monolithic system from scratch is neither realistic nor necessary. Besides the immature design and lack of time testing, resulting in unreliable system performance and quality, the excessively long design cycle would also diminish its commercial value. To accelerate the monolithic system design cycle and improve system reliability, the most effective approach is currently through licensing, using mature and optimized IP core modules for design integration and secondary development, and embedding these IP core modules into the SOC using Glue Logic Technology (GLT). IP core modules are the foundation of monolithic system design; the choice of which level of IP core modules to purchase depends on a balance of existing resources, time, funding, and other conditions. Purchasing hard IP core modules carries the lowest risk but the highest cost, which is inevitable. In general, purchasing IP kernel modules can reduce development risks and save development costs, as the cost of purchasing IP kernel modules is usually lower than the cost of designing and verifying them independently. Of course, not all required IP kernel modules are available on the market. To monopolize the market, some companies are unwilling to license their key IP kernel modules (at least temporarily). Such IP kernel modules must be developed in-house. Each of these three levels has its own application scope. From an application development perspective, the first two methods will be used for a considerable period. The third-level design method is only suitable for designing simple single-chip systems for general application personnel. Complex single-chip systems can only be designed and implemented by certain large semiconductor manufacturers, and single-chip systems implemented using this method are only worth developing for widely used, large-scale application systems. Some application systems are not suitable for single-chip implementation due to technical or commercial reasons. When these are commercially available as single-chip systems, application personnel only need to know how to select them. Therefore, the three levels of design methods will coexist, and the latter will not simply replace the former. Junior application designers primarily use the first method; experienced designers primarily use the second method; and highly professional designers use the third method for designing and applying simple single-chip systems. However, all designers can utilize dedicated single-chip systems designed using the third method from major semiconductor manufacturers. IV. Conclusion Currently, in China, the three levels of design are respectively characterized by "surface," "line," and "point" approaches. Electronic information system designers accustomed to the first-level design method need to gradually transition and develop towards the second level; the second-level design method needs to gradually evolve from "line" to "surface"; the third-level design method requires relevant national departments to organize various forces to tackle key challenges and coordinate development based on IT development strategies and plans. The third-level design method needs to gradually evolve from "point" to "line."