Introduction Speed ​​measurement is one of the fundamental problems in control engineering. In many cases, speed measurement signals need to be transmitted over long distances. A primary method to achieve this is using a System-on-a-Chip (SoC). Its rich peripherals have changed the perception of hardware and software. Building a hardware system has become about understanding and mastering the hardware structure, and software programming has shifted from primarily algorithm development to primarily component configuration, offering simplicity and completeness, reflecting the technological advantages of the chip. The TMS320LF2407 DSP chip, a SoC-type chip, embodies this with its simple and integrated design in speed measurement and remote transmission applications. 1. Relevant System Structure The event manager and CAN controller modules integrated into the TMS320LF2407 facilitate speed measurement and remote transmission. The TMS320LF2407 has two event managers, EVA and EVB, each with three capture units. These correspond to six capture input pins CAPX (for EVA, X=1, 2, 3; for EVB, X=4, 5, 6). The six capture input pins are shared with QEP1/IOPA3, QEP2/IOPA4, IOPA5, QEP3/IOPE37, QEP4/IOPF1, and IOPF1, respectively. When a selected transition is detected on the capture input pin CAPX, the count value of the selected GP timer is captured and stored in a 2-level deep FIFO stack. The TMS320LF2407 CAN controller module includes mailboxes and corresponding control/status registers. There are six mailboxes in total: two receive mailboxes (MBOX0, 1), two transmit mailboxes (MBOX4, 5), and two mailboxes that can be configured as either receive or transmit mailboxes (MBOX2, 3). The TMS320LF2407 CAN controller module fully supports the CAN 2.0B protocol. Typically, speed sensor systems output digital speed pulse signals. Therefore, this can be added to the capture pins of the TMS320LF2407 DSP chip. The TMS320LF2407 chip's capture unit measures the period of the input pulse, and the built-in CAN bus controller unit then sends out a CAN period signal, achieving integrated speed measurement and remote transmission. 2 System Configuration 2.1 Configuration of the Capture Unit and Corresponding Timers The working principle of the TMS320LF2407 capture unit is as follows: the period is measured by counting with the corresponding timer, using the rising edge, falling edge, or rising-falling edge of the input pulse as the boundary. The count value is captured and sent to a corresponding level-two deep capture stack FIF0. Therefore, configuration operations are involved for both the capture and timer parts. The capture operations that need to be configured are: configuring the corresponding pin as a capture input in the I/O port multiplexing control register MCRx (x=A, B, or c); selecting (enabling) the capture unit, selecting (enabling) the corresponding timer, and edge selection (rising edge, falling edge, or rising-falling edge) in the capture control register CAPCONA/B; and setting the interrupt control status in the interrupt flag register EVA/BIFRX and interrupt mask register EVA/BIMRX. The operations requiring timer configuration include: clearing a single general-purpose timer TXCNT; setting the operation and counting direction of the corresponding timer in the global general-purpose timer control register GPTCONA/B; setting the comparison period in a single general-purpose timer period control register TXPR; and setting the counting operation mode in a single general-purpose timer control register TXCON. The comparison period set in the period control register TXPR should be greater than the period of the input pulse signal. If the period of the input pulse signal is unknown, it should be set to the maximum value. When the measurement period exceeds the maximum capture time, a timer overflow method plus software counting is used to resolve the issue. 2.2 Retrieving and Transferring the Capture Period The capture period stored in the capture stack FIFO can be retrieved using two methods: interrupt and polling. The interrupt delay time of the event manager where the capture unit is located is 20 CPU cycles (typical), or 25 CPU cycles (minimum protection), or 8 CPU cycles (single interrupt), or 16 CPU cycles (not considering memory space). In specific designs, the interrupt delay time is set to a certain value. When the interrupt handler is usually very short, the interrupt time is mainly determined by the interrupt delay time. For system expansion, even for a single peripheral, it is still advisable to use the interrupt method rather than the polling method. 2.3 CAN Controller Module and Bit Timer Configuration The configuration of the CAN controller module includes initializing the mailbox, setting the bit timer, and data transmission and reception. See reference [1] for relevant content. Here we introduce the setting of the bit timer. The setting of the bit timer determines the baud rate of the bus transmission signal and is the core configuration issue of the CAN controller module. The TMS320LF2407 has two bit control registers, BCR1 and BCR2. They can only be configured when the CAN controller is in reset mode (i.e., CCR=1). The bit control register BCR2 includes the baud rate prescaler bit BRP [7-0], which is used to determine the time slice TQ of the CAN controller as the reference time for bit control. The bit control register BCR2 includes the synchronization jump width selection bit SJW[1-0], the sampling number selection bit SAM[7], the time period 1 TSEG1[3-0] which includes the propagation delay time period (PROG SEG) and the phase delay time period 1 (PHASE SEG1), and the time period 2 TSEG2[2-0] which determines the phase delay time period 2 (PHASE SEG2). 3 Design Example The basic setup of this example is to select the capture unit 4 (CAP4) to capture the input pulse width, and the general-purpose timer 3 of the event manager EVB counts the pulses. The capture count value is taken from the FIFO stack and sent to the temporary register CAP4TEMP for expansion. Then it is sent from CAP4TEMP to mailbox 3 and sent via CANTX/IOPC6 and CANRX/IOPC7, as shown in Figure 1. 3.1 The capture unit is interrupt mode and the CAN controller is polling mode. First, the system is initialized, including disabling interrupts, clearing flags, enabling the 4th level interrupt INT4 containing the capture unit with the system clock 20MHz, and then the capture unit and CAN controller are initialized. The relevant content has been described previously. Since the capture unit is in interrupt mode, the operation of retrieving the capture cycle value from the capture stack FIFO is performed in the capture unit's interrupt handler; while the CAN controller is in polling mode, the capture flag needs to be checked cyclically in the main program. After confirming capture, the capture cycle value is retrieved from the temporary register CAP4TEMP and sent to mailbox 3. It is worth mentioning that since the capture cycle value is 16 bits, the data to be transmitted is 2 bytes. Therefore, DL=2 for the transmit controller MSGCTRL3. The program flow for this situation is shown in Figure 2. 3.2 Capture Unit Interrupt Handling Includes CAN Controller Information Transmission As mentioned earlier, when the CAN controller is in polling mode, the CAN controller's operation program is complex and located in the main program, which is not conducive to the expansion of the main program and the addition of peripherals; therefore, the CAN controller information transmission can be set in the capture unit interrupt handling, making the main program very simple. In this case, the capture unit interrupt handler includes both capture cycle retrieval and CAN information transmission. Due to the reduction of judgments and loops, CAN information transmission becomes simpler. The interrupt handler for the capture unit is as follows: CAP4_ISR LDP #DP EVB LACL CAP4FIFO ; Get capture stack value LDP DP_USER SACL CAP4TEMP ; Move capture value into temporary register LDP #DP EVB SPLK #0, T3CNT ; Clear T3 counter value to reset LDP #DP_CAN SPLK #0000H, MDER ; Disable mailbox SPLK #0100H, MCR ; CDR=I, data change request LDP #5 LACL CAP4TEMP ; Get capture value LDP #DP_CAN2 SACL MBX3A ; Move capture value into mailbox 3 LDP #DP_CAN SPLK #0880H, MCR ; DBO=1, CDR=0, ABO=1, STM=0 SPLK #08H, MDER ; MD3=0, ME3=1, mailbox 3 transmit enable LDP #DP CAN SPLK #0020H, TCR; Mailbox 3 sends request W_TA3 LDP #DP_CAN BIT TCR, 2; Mailbox 3 sends response TA3 (bit 13) = 1 BCND W_TA3, NTC; Waiting for response LDP #DP_CAN SPLK #2000h, TCR; Send response TA3, write 1, reset CLRC INTM; Enable interrupt RET 4 Conclusion Analysis and design show that by utilizing the features of the TMS320LF407 SoC chip and appropriately configuring the corresponding units, faster control functions can be achieved simply and effectively, reflecting the control function and the inevitable development trend of control implementation methods. Debugging and application demonstrate that this method is correct and effective.