Abstract : This paper introduces the interface between Analog Devices' TS101S DSP and PCI, analyzes its hardware composition and operation, and presents the hardware principle of the interface circuit between TS101S and PCI9054. Keywords : Digital Signal Processor, TS101S, PCI9054, Interface 1 Introduction The DSP+PCI digital signal processing scheme can utilize the powerful functions of a PC to realize the operation control, data analysis, and operation monitoring of the DSP. For example, the system no longer needs a dedicated human-machine interface (such as a keyboard or monitor); it only needs to upload data to the PC for display. The PC can also be used as the master controller to realize the control of the uplink and downlink of data streams and the selection of working modes. The DSP+PCI scheme can fully meet the application needs of digital image, voice processing, high-speed real-time data processing, etc., and provides a solution for the low-cost implementation of DSP systems. 2 Introduction to TS101S DSP This system uses the high-performance TIGER SHARC 101S (TS101S) from Analog Devices as the main processor. The TS101S processor hijacks 32-bit and 64-bit floating-point operations, as well as 8, 16, 32, and 64-bit fixed-point operations. Its static overscalar architecture allows it to execute up to four instructions per cycle, performing 24 16-bit fixed-point operations and six floating-point operations. Internally, it has three independent 128-bit wide data buses, each connecting to one of three 2Mbit internal memory blocks, providing 4 bytes of data, instruction, and I/O access and 14.4 Gbyte/s of internal memory bandwidth. Running at a 300MHz clock speed, its core instruction cycle is 3.3ns. Leveraging its Single Instruction Multiple Data (SID) feature, the TS101S can perform 2.4 billion 40-bit MAC operations or 600 million 80-bit MAC operations per second. Running at a 300MHz clock speed, it completes a 1024-point complex FFT (radix-2) in just 32.78μs and a 1024-point input 50-tap FIR in 91.67μs. The TS101S boasts powerful link port transmission capabilities, with each link port achieving a transmission speed of 250 Mbyte/s. The total link data rate reaches 1 Gbyte/s (4 link ports), exceeding the external port's transmission rate (800 Mbyte/s). 3. Introduction to PCI The PCI (Peripheral Component Interconnect) bus is a high-performance local bus independent of a specific processor. Therefore, PCI device development can be independent of the processor. Specifically, a bridge circuit (PCI bridge) manages this layer and enables data transfer between the upper and lower layers. A PCI bridge can be described as a logical interface that implements address mapping, protocol conversion, and data buffering between general-purpose buses and the PCI bus. 3.1 Implementation of PCI Bridges Developers can design the interface according to the electrical characteristics and timing requirements defined in the PCI bus specification. One approach is to use programmable logic devices (FPGAs/CPLDs) to design according to the actual functional requirements. This method is low-cost and highly flexible, but requires a thorough understanding of the PCI bus protocol or the provision of PCI interface function modules by the programmable logic device manufacturer. Because the PCI bus specification is relatively complex, most users choose dedicated PCI interface circuits, requiring only an understanding of the application layer, without needing to understand the underlying PCI bus protocol in detail. Therefore, the system described in this paper adopts the latter approach, using the PCI9054 from PLX, a commonly used PCI interface circuit on the market. 3.2 PCI9054 The PCI9054 employs advanced PLX data pipeline architecture technology and is a 32-bit, 33MHz PCI bus master I/O accelerator, conforming to PCI local bus specification version 2.2, with M, C, and J modes. It can be selected for different processors and local bus characteristics, minimizing intermediate logic; it has an optional serial E2PROM interface, and the local bus clock can be asynchronous with the PCI clock. The PCI9054 has six programmable FIFOs internally to achieve zero-wait burst transfers and asynchronous operation between the local bus and the PCI bus, supporting master mode, slave mode, and DMA transfer mode. It is powerful and can be applied to adapter cards and embedded systems. 4 DSP+PCI Application Example The composition of the DSP+PCI digital signal processing system is shown in Figure 1. The module signal is first input to the analog-to-digital converter, then latched by the CPLD to DSP1, then to DSP2 via the link port, and finally transmitted to the PC via the PCI9054 after data processing. The CPLD also serves as the interface logic converter between the PCI9054 and the TS101S. A dual-port RAM is placed between the PCI9054 and a single TS101S as a buffer. The DSPs use an EPROM loading scheme. A key feature of this system is its simplicity in implementing system functions; therefore, it employs a port interconnection method between DSPs. This requires only 10 signal lines per link port, compared to over 100 signal lines for a bus interconnection method, significantly simplifying the PCB board complexity. Two link channels are reserved between the two DSPs, with a total data rate of up to 500 Mbyte/s. Port interconnection is a unique feature of ADSP systems and a major reason why ADSP processors can be used to assemble multiple high-performance signal processors at low cost. 4.1 TS101S and PCI9054 Interface Since the TS101S lacks a dedicated PCI interface, and the PCI9054 can only seamlessly connect with Motrola circuits such as the MPC850 or Power QUICC in M ​​mode, a programmable logic device is needed for logic conversion between the TS101S and PCI9054. Considering development cycle time, a simpler communication method is adopted: a dual-port RAM is inserted between the DSP and the PCI bridge. One end of the dual-port RAM connects to the ISI101S, and the other end connects to the PCI9054. Data is converted through the dual-port RAM and used as a common access buffer. This makes access between the PCI bridge and the DSP indirect, significantly reducing the timing requirements of the PCI. Only a small number of signals are needed between the DSP and PCI for logic conversion via the CPLD, eliminating the need for bus arbitration. This method simplifies timing, reduces control signals, simplifies DSP and CPLD programming, and makes application more convenient. The dual-port RAM is model IDT70261, with a capacity of 16k×16bit. The PCI9054 operates in slave mode, driven by the PC, with the digital signal processor acting as the host on the local side. Read and write operations are performed via the shared dual-port RAM. In terms of timing, only a few simple control signals are needed for handshaking to achieve bidirectional data transmission. The PC actively issues read and write commands, enabling single-byte read and write operations as needed. This method is sufficient for most systems. The specific interface circuit is shown in Figure 2. The signal functions on the local bus side of the PIC9054 are as follows: LHOLD: Bus request signal, driven by the PCI9054, active high, indicating that it is using the local bus. LHOLDA: Bus request acknowledge, driven by the local device, active for one cycle after LHOLD becomes active, and only becomes inactive after LHOLD becomes inactive, indicating to the PCI9054 that the local device is not using the bus. ADS: Address threshold signal, active low, indicates the start of a bus access cycle. It is active on the first clock cycle and lasts for one LCLK, after which the address lines are active. USERo: User output signal, driven by the PCI9054 and introduced into the CPLD as an external interrupt request for the DSP. USERi: User input signal, driven by the external device. The PCI9054 can query signals sent by external devices. LW/R: Read/write signal, driven by the PCI9054. READY: Input signal in slave mode. When an access cycle ends, the device on the LOCAL side sends a READY signal to the PCI9054, indicating that the current access is complete and the next round of access can begin. 4.2 System Operation Mode Since this system uses RAM buffering, only handshake signals are needed between the PCI9054 and the DSP. The handshake is achieved through the DSP's external interrupt IRQ and flag pin FLAG, and the PCI9054's user input/output USERi/USERo, enabling basic single-byte read/write operations. For more complex functions, control words can be added. The address mapping uses a 16-bit data width for the dual-port RAM. PCI9054 addresses LA1-LA14 are connected to RAM addresses ADD0-ADD13 respectively. The offset address in the PCI mapping space is 0-7FFEH, with even addresses being valid. LA15, after being introduced into the CPLD, can be used as the chip select signal for the dual-port RAM. The communication establishment process involves the PCI9054 sending the LHOLD signal, and the CPLD returning the LHOLDA signal. The PCI9054 then sends the ADS signal, indicating the start of a read/write operation. At this time, the CPLD latches the read/write signal LW/R and converts it to the RAM's R/W or OE signal. The CPLD sends a READY invalid signal to the PCI9054, keeping it in a waiting state. The signal handshake process is as follows: PCI9054 writes data to RAM → PCI9054 sends a handshake request to the CPLD via USER0 → CPLD sends an interrupt signal to the DSP's IRQ → DSP responds to the interrupt → DSP reads RAM data. The DSP writes data to RAM → The DSP sends a handshake request to the CPLD via the FLAG → The CPLD sends an interrupt signal to the PCI9054's USERi → The PCI9054 detects the interrupt → Data is sent to the PCI9054 or RAM. The timing is shown in Figure 3. The program of CPLD is as follows: Library IEEE; Use IEEE.STD_LOGIC_1164.all; Use IEEE.STD_LOGIC_unsigned.all; STD_LOGIC; READY:OUT STD_LOGIC; OE:OUT STD_LOGIC; RW:OUT STD_LOGIC); END PCI; ARCHITECTURE PCI_arch OF PCI IS SIGNAL signal_0:STD_LOGIC; BEGIN PROCESS (LCLK) BEGIN IF LCLK'EVENT AND LCLK='1'THEN IF LHOLD='1'THEN IF ADS='0'THEN Signal_0<='1'; ELSIF ADS='1'THEN Signal_0<='0'; END IF; END IF; END IF; IF LCLK'EVENT AND LCLK='1'THEN IF LHOLD='1'THEN IF LWR='0'THEN OE<='0'; RW<='1'; RW<='0'; END IF; END IF; END IF; IF LCLK'EVENT AND LCLK='0'THEN IF LHOLD='1'THEN IF signal_0='1'THEN READY<='0'; BEGIN IF LCLK'EVENT AND LCLK='0' THEN IF LHOLD='1' THEN LHOLDA<='1'; ELSIF LHOLD='0' THEN LHOLDA<='0'; END IF; END IF; END PROCESS; END PCI_arch; 5 Conclusion The DSP-PCI bus interface scheme introduced in this paper is flexible and simple, reducing board layout complexity, simplifying the timing requirements of the PCI bus, and shortening the development cycle. The data processing system designed using this scheme operates stably and has been applied in the field of low-frequency signal detection.