Abstract: This paper designs and implements a bit error rate tester (BERT) for measuring baseband transmission channels. The working principle of the main modules is explained, and a new method for extracting the synchronization clock using an integral phase detection method is proposed. This method can improve the accuracy of the synchronization clock, thereby improving the accuracy of bit error rate measurement. Keywords: Bit error rate tester; FPGA; Phase detector; Digital phase-locked loop Introduction A bit error rate tester is a fundamental measuring instrument for evaluating channel performance. This paper introduces a bit error rate tester that combines the characteristics of FPGA and adopts a novel integral phase detection structure. A new bit error rate testing method is proposed. After multiple tests, the scheme is feasible, and the designed system is stable. The bit error rate tester designed in this paper consists of two parts: a transmitter and a receiver. 1. Transmitter The main function of the transmitter is to generate a pseudo-random m-sequence with random characteristics, implemented by VHDL programming through FPGA. The principle of pseudo-random sequence generation is as follows: Figure 1 Pseudo-random sequence generation principle diagram Wherein, ak-i is the state of each shift register, Ci corresponds to the feedback coefficient of each register, 1 indicates participation in feedback, and 0 indicates no participation in feedback. The feedback function is: Once the series n and the feedback coefficient are determined, the output sequence of the feedback shift register is determined. An important property of the m-sequence is that the cyclic shift of any m-sequence is still an m-sequence with a sequence length of m = 2n-1. 2. Receiver The receiver is mainly composed of a clock synchronization module and a state synchronization module. Its functional block diagram is shown in Figure 2. Figure 2 Functional block diagram of the error error receiver 2.1 Clock extraction module The clock extraction method used in this unit is implemented by a new integral phase detection. By integrating the symbol within one clock cycle, the lead and lag are judged, thereby greatly reducing the possibility of mistuning caused by the appearance of interference signals. The principle diagram of clock extraction is as follows: Figure 3 Principle diagram of clock extraction (1) Phase detector The characteristic of the lead-lag type digital phase detector is that it outputs a quantity that indicates whether the local estimated signal leads or lags the input signal. If the local estimated signal leads the input signal, it outputs a "lead pulse" so as to use the "lead pulse" to control the phase of the local estimated signal to be pushed back. Conversely, it outputs a "hysteresis pulse" and shifts the phase of the locally estimated signal forward. Lead-lag digital phase detectors can be divided into differentiating and integrating types. Because integrating lead-lag digital phase detectors have excellent anti-interference performance, this design uses an integrating lead-lag digital phase detector. In the integrating lead-lag digital phase detector, the rising edge of the local clock is the cleaning moment for in-phase integration. When the rising edge arrives, the in-phase counter starts counting under the local high-frequency clock. When the input symbol is "1", the counter increments by 1 for each high-frequency pulse; when the input symbol is "0", the counter decrements by 1 for each high-frequency pulse. When the next rising edge arrives, the count value is output, and the counter is cleared. The counter restarts counting under a high-frequency pulse. The falling edge of the local clock is the cleaning time for the mid-phase integrator. When the falling edge arrives, under the same high-frequency clock as above, the mid-phase integrator counter starts counting. When the symbol is "1", the counter increments by 1; when the symbol is "0", the counter decrements by 1. When the next falling edge arrives, the count value is output, and the counter is cleared, restarting the counting. Under accurate synchronization, the integration interval of the in-phase integrator coincides exactly with the width of one received symbol. The in-phase integrator counter outputs ±T (+T indicates symbol 1, -T indicates symbol 0), while the mid-phase integrator outputs 0 or ±T. If the symbol changes from 0 to 1 or 1 to 0 within the mid-phase integration period, the mid-phase integrator output is 0. If the symbol does not flip within the mid-phase integration period and remains "1", the mid-phase integrator counter outputs T. If the symbol remains "0", the mid-phase integrator counter outputs -T. If the locally estimated clock leads the input symbol, when the output of the in-phase integrator counter is greater than 0, the output of the subsequent intermediate-phase integrator counter will also be greater than 0; when the output of the in-phase integrator counter is less than 0, the output of the subsequent intermediate-phase integrator counter will also be less than 0. When the output of the in-phase integrator counter is +T or -T, and the output of the subsequent intermediate-phase integrator counter is also +T or -T, it indicates a continuous "1" or "0" state, and the lead or lag flag is 0. If the locally estimated clock lags the input symbol, when the output of the in-phase integrator counter is greater than 0, the output of the subsequent intermediate-phase integrator counter will be less than 0; when the output of the in-phase integrator counter is less than 0, the output of the subsequent intermediate-phase integrator counter will be greater than 0. When the falling edge arrives, the output of the in-phase counter is checked first. If it is 0, and the output of the intermediate-phase counter is 0, it means that detection has not started yet, and there is no lead or lag information. If the output of the intermediate-phase counter is not 0, it means that the locally estimated clock is exactly orthogonal to the clock to be detected, and is at the boundary between lead and lag, where lead processing is performed. If the output of the in-phase counter is not 0, and the output of the intermediate phase counter is 0, it means that the two clocks are synchronized, so there is no lead or lag information. If the output of the intermediate phase counter is ±20, which is the length of the entire symbol, it means that the intermediate phase counting process is always "1" or "0". If there is a continuous "1" or "0" state, it is also considered that there is no lead or lag to prevent misoperation. If the output of the intermediate phase counter is not 0 or the entire symbol, the sign bit of the output of the in-phase counter and the output of the intermediate phase counter are XORed. That is, if the signs are the same, it means lead; if the signs are different, it means lag. (2) Dual-phase high-frequency clock source and stop control circuit The dual-phase high-frequency clock source forms two narrow pulse signals, which are exactly 180 degrees apart. The stop control circuit is mainly composed of add gate and stop gate. When a lead pulse comes, it is added to the stop gate and a crystal pulse is subtracted. In this way, the output pulse phase of the frequency divider is delayed by 1/20 period. When a delayed pulse arrives, it is added to the add gate, which controls the add gate to open and adds a crystal pulse to the OR gate. Since the phase difference between the crystal oscillator signal added to the add gate and the crystal oscillator signal added to the knock gate is 180 degrees, when a crystal oscillator pulse is added from the add gate to the OR gate, it is equivalent to inserting a narrow pulse in the middle of the crystal oscillator signal output by the knock gate, which adds a pulse to the input of the frequency divider, so that the output phase of the frequency divider is advanced by 1/20 cycle. Thus, bit synchronization is achieved. 2.2 State Synchronization Module The state synchronization module mainly includes a bit-by-bit comparison detection module, a bit error statistics and threshold detection module, a parallel input and state control module, a state parallel comparison module, and a "1" consecutive state counter module. (1) Bit error statistics and threshold detection module: under the clock beat, the bit error pulses are counted, and the clock pulses are counted at the same time. If the number of bit errors accounts for more than 30% of the number of clock pulses, the bit error rate is considered to be very high, indicating that the states of the two sequences of the system are not synchronized. At this time, the threshold detector will output a low level, and a synchronization search is required. If the proportion of bit errors is low, the output is high, indicating that the system is now synchronized and no longer needs to perform a synchronization search. (2) Parallel input and state control module: When the control terminal is “0”, the module sends the two sets of parallel input signals to the output terminal as before. When it is “1”, all output signals are set to “0”. At this time, all input signals of the state comparator are at the same potential and output a high level to indicate that the system is synchronized and enters the synchronization protection state. (3) Continuous “1” state counter module: This module has two functions: one is to count the continuous “1” state output of the state comparator. When the counter count reaches the set value, the counter output is “1” and controls the “parallel input and state control” circuit to make each parallel output position “0”. In this way, each input bit of the state comparator is “0”, and its output is “1”, indicating that the state is synchronized; if the state is not synchronized, the output of the continuous “1” counter is always “0”. The other function of the continuous “1” counter is that the bit error counter counts only when its output is “1”. If a state synchronization failure occurs after the entire system has been synchronized, the output state control of the bit error rate (BER) statistics and threshold circuit controls a "1" counter. When the number of consecutive "1"s reaches a set number, the output is "1" and sent to the parallel input and state controller, setting its output to "0" to achieve synchronization protection control. 3. Conclusion The advantages of the BER meter designed in this paper are that it can be easily applied to the testing of baseband transmission channels, accurately measuring the transmission errors of baseband transmission channels, and at a low cost.