Abstract: This paper introduces an information acquisition and control device for safety-critical systems designed using a microcontroller, PSD, CPLD, and voltage conditioning circuit as the main components. Actual testing shows that this design method is not only efficient and feasible, but also a way to ensure the miniaturization, integration, and intelligence of the testing device and improve the reliability of the testing system. Keywords: Intelligent testing, Safety-critical system, Microcontroller, Integrated testing. Safety-critical systems (SCS) refer to systems whose functional failure would cause significant loss of life and property and potentially severe environmental damage. They are widely present in many fields such as aerospace, energy, and defense. Many safety-critical systems have strong multi-input-multi-output coupling, time-varying parameters, and nonlinear characteristics. The rapid development of electronic technology has led to increasingly higher integration and complexity of SCS electronic systems, and the controlled objects are becoming increasingly complex. This places higher demands on the safety and operational normality assessment and decision-making of the system; some key components even require zero failures throughout their service life. SCS test data is the basis for comprehensive, accurate, and intelligent assessment, fault diagnosis, and decision-making. Furthermore, many safety-critical systems have strict size and weight limitations, requiring embedded test systems running on them to be small, lightweight, and fully functional, while also possessing high reliability and intelligence to ensure test accuracy and improve test credibility. Therefore, small size and reliability are the most basic requirements for SCS testing, and the secure, reliable, and high-speed transmission of test data is also a key requirement. This paper introduces a small, highly integrated intelligent test device applied to a comprehensive test system for electronic equipment in a type of safety-critical system. Its function is to perform real-time control and measurement of important states and parameters of the safety-critical system, completing numerous functions such as large-scale data acquisition and processing, and receiving and transmitting control signals. Due to the very high requirements on the system's computing speed, interface resources, stability, and cost, its test data, analysis curves, displayed charts, and indication results are crucial for analyzing and judging the performance and operating status of the safety-critical system, while also providing a basis and means for related decision-making, command, and control. 1. System Design and Working Principle 1.1 System Composition The small, highly integrated intelligent testing device adopts an 80C196 microcontroller + PSD + CPLD structure, plus an analog signal matching circuit, enabling the acquisition of analog and digital quantities, simplifying the system's circuit design. Both the PSD and CPLD are in-system programmable devices, allowing for the conversion of a large amount of hardware design into software design, and facilitating I/O interface expansion. The host computer mainly transmits test data, sets parameters, and controls the testing system through a standard interface. SCS electronic integrated testing mainly includes SCS key component testing, ground peripheral measurement and control, and its data transmission and processing. Its functional block diagram is shown in Figure 1. 1.2 Composition of the Small Intelligent Measurement and Control Device The small intelligent measurement and control device mainly includes a data acquisition module, a static detection module, a remote parameter setting module, and a data transmission module. Because SCS has strict size and weight requirements for electronic control components, the measurement and control device should be designed according to the system requirements, minimizing size and weight while ensuring complete functionality to guarantee the system's feasibility. Many optimizations and improvements were made during the design process of the testing device. Its basic architecture adopts a microcontroller plus peripheral interface module structure. In designing the hardware of the data acquisition system, highly integrated devices were employed, including the 80C196 microcontroller, programmable peripheral devices (PSDs), and complex programmable logic arrays (CPLDs), improving system integration and enhancing hardware reliability and flexibility. The peripheral interface module utilizes the complex programmable gate array (CPLD) MAX7256, further software-based in the hardware design. A single CPLD replaces multiple 74-series devices, such as 138 decoders, multiplexers, 244 drivers, AND gates, and OR gates, significantly reducing board size. The programmability of the CPLD allows for greater design flexibility. The MAX7256 has 5000 gates, 256 macrocells, 16 logic array blocks, and 164 I/O ports, supporting multi-voltage I/O interfaces to meet system requirements and provide redundancy. During the design phase, the CPLD design was simulated using EDA tools, including functional, timing, and EMC/EMI simulations, ensuring thorough testing and verification before PCB board completion. In addition, the PSD4235, a microcontroller peripheral interface device with higher integration, was selected. The PSD4235 chip is a newly launched product in WSI's PSD4000 series, providing in-system programmable concurrent flash memory, SRAM, programmable logic, and additional I/O for 16-bit and 32-bit microcontrollers and DSPs. It integrates 4MB of flash memory, 256Kbit of sub-flash memory for boot data, 256Kbit of SRAM, a CPLD with 16 output microcells and 24 input microcells, a decoding PLD, 52 individually configurable I/O ports, a JTAG serial interface, and a low-power programmable power management unit supporting power-down mode. Address allocation and logic decoding for each interface are implemented by dedicated software PSDSoft Express. The PSD4000 series devices are in-application re-programming (IAP), meaning they can be reprogrammed remotely in the field without affecting system operation. This functionality is particularly useful for systems that require on-site code/data updates, such as GPS, automotive control systems, and medical instruments. The circuit diagram of the measurement and control device is shown in Figure 2. 1.3 Signal Acquisition In real-time measurement and control systems, signal acquisition requires reliable, accurate, and rapid completion. The measured loops typically number in the dozens or hundreds, and the types of acquired signals are diverse, including analog and digital signals. Therefore, the testing work must have strong real-time performance, and the anti-interference capability of data acquisition is also highly demanding. It is precisely because of the increasingly complex requirements for data acquisition systems that intelligent, small-scale safety-critical system acquisition modules can become the core of the measurement and control system. Data testing mainly includes testing the voltage, program actions (delay time or constant parameters), oscillation waveforms, and pulse trains of various key components of the SCS. The design focuses on reliability and real-time performance. The reliability of data acquisition is crucial; only with high reliability can the correctness of data acquisition be guaranteed. Therefore, the design fully considers the anti-interference capability of the testing process, improving the reliability of the test. The structure of the data acquisition module is shown in Figure 3. The analog quantity measurement uses the analog quantity measurement interface of the 80C196 microcontroller. The 80C196 has a total of 8 A/D ports. It is necessary to use a multi-channel switch to switch the A/D conversion circuit of each circuit under test in turn to achieve the purpose of time-division processing. Since the signal strength, amplitude and impedance matching circuit are different, the following processing was carried out in the design: (1) The voltage signals are classified. Those that do not require amplifiers belong to one category, and within this category, they are further subdivided into voltage value range classifications. Because the 80C196 microcontroller requires the acquisition level to be within 5V, if voltage division and RC filtering are designed for each voltage channel, a large number of resistors and capacitors will be used, which is not conducive to miniaturization. Therefore, they are classified according to voltage amplitude. Impedance matching is also very important. The same type of RC filtering network is placed at the output end of the multi-channel switch, saving a large number of resistors and capacitors. Select 4-channel, 8-channel or 16-channel multi-channel switches as needed, such as CD4051, CD5052, MAX396 or MAX397, etc. (2) For small signals, an amplifier should be set before the multiplexer for each channel. A programmable amplifier should be set after the multiplexer, and the gain of the amplifier should be controlled by the microcontroller to meet the different gain requirements of each channel signal. (3) For switch and digital signals, adjust to the level that meets the input requirements of the CPLD. Design a multiplexer inside the CPLD to convert the number of measurement channels and input 8 channels at a time to the 80C196 microcontroller port. (4) For frequency signals, adjust to the TTL level that meets the input requirements of the microcontroller and input directly to the microcontroller port for measurement. (5) For signals with strong signals and large interference, opto-isolation is required to avoid affecting the microcontroller test circuit. 1.4 CPLD Circuit Design PSD devices already have a small number of CPLD macrocells. If the test system is not complicated and the I/O ports are sufficient, the two-chip system of PSD+CPU can complete the task well, so there is no need to add CPLD devices. When there are many external channels for testing and control, requiring a large number of digital I/O ports, chip selects, digital multiplexers, tri-state gates, and decoding circuits, adding only one CPLD device can solve the problem and improve the system integration. Both FPGA and CPLD are programmable ASIC devices. Due to the differences in their structures, FPGA and CPLD have their own characteristics: (1) CPLD is suitable for implementing various operations and combinational logic, while FPGA is suitable for implementing sequential logic. (2) The timing characteristics of CPLD are more stable than those of FPGA. The wiring structure of CPLD determines that its timing delay is stable and predictable, while the segmented wiring structure of FPGA makes it difficult to predict its timing delay, so CPLD is faster than FPGA. (3) FPGA has greater flexibility in programming than CPLD. CPLD is programmed by modifying logic functions with fixed internal interconnections, while FPGA is mainly programmed by changing the internal wiring. (4) FPGA has a higher integration level than CPLD and is suitable for more complex wiring structures and logic implementations, so the number of programmable logic units in FPGA is much larger than that in CPLD. (5) CPLD is easier to use than FPGA. CPLD programming uses E2PROM or Flash technology and can be encrypted. No additional external storage element is required during use. FPGA programming uses SRAM technology and uses external storage element to store the program, which is more complicated. In addition, the circuit information is stored in an external chip, which makes the security of FPGA worse than that of CPLD. The circuit data can be easily read by others and the circuit can be easily stolen. It is not suitable for systems with high security requirements. (6) In terms of programming method, CPLD is mainly based on E2PROM or Flash storage programming. The number of programmable times is greater than 10,000. The advantage is that the programming information will not be lost when the system is powered off. FPGA is mostly based on SRAM programming. The programming information will be lost when the system is powered off. Therefore, the system must read the programming information from the external memory device into the FPGA's SRAM every time it is powered on. Its advantage is that the number of programmable times is unlimited and the program can be easily changed at any time during the development process. Its disadvantage is that the program is easily interfered with when the system is powered on. The above factors should be considered in the design to determine whether to choose CPLD or FPGA. According to the test function requirements, the internal structure of the CPLD chip designed in this system is shown in Figure 4. In CPLD design, VHDL is used as the primary design language, which is one of the mainstream methods in current ASIC design. VHDL implementation offers high efficiency, convenience, and portability, while pure hardware circuit design lacks flexibility, is inconvenient to modify, and often results in the scrapping of printed circuit boards. This software-based hardware design allows for adaptation modifications to only a portion of the corresponding circuit software when the access points of the device under test change or are added or removed. The underlying hardware circuit and upper-level application software require minimal or no changes, significantly reducing system maintenance costs. During the CPLD design process, software simulation is performed simultaneously on a computer, ensuring that simulation testing and functional behavior verification are integrated throughout the design process. This guarantees the correctness and reliability of all functions and ensures the design quality of the final product. In system design, the CPLD can perform additional functions as needed, such as integrating some functions of the 80C196 microcontroller, primarily the testing components, including serial interface, data encoding/verification, frame construction, timing transmission, and data exchange with external test computers. Through long-term accumulation, a large number of reusable IP modules are available, making system development and design faster. 2. Intelligent and Reliable Design Intelligent measurement and control of system information is mainly reflected in two aspects: First, it must have a learning and recording function, capable of automatically adjusting its control parameters based on the initialization or measured values ​​of the information channel; second, it must be able to adjust its channel number, number of channels, acquisition time, transmission bytes, and control mode according to received commands. The small intelligent testing device introduced in this paper can not only quickly adjust the test content according to needs, but also has functions such as static inspection, parameter binding, and data provision. The data obtained from its tests can be transmitted to the peripheral test receiving equipment via RS-485 serial communication bus or wireless means. Since data transmission, test data encapsulation, and channel selection are all implemented by software, it has a high degree of intelligence and is easy to use. During the transmission of measurement and control data, different information formats are used for different tasks, requiring different data processing programs. Communication protocols and data processing protocols should be constructed according to the communication content between the peripheral measurement and control system and the SCS intelligent testing device, processing different data according to different information types (control commands), while the packetization and transmission of information frames are handled by the transmission module. Strong electromagnetic interference is common in test sites, entering the system through conduction and radiation from power and signal lines. To ensure reliable system operation, a combination of hardware and software anti-interference techniques is employed. RC filtering, high/low level clamping, and isolation techniques are used in the input channels to effectively suppress various high-frequency interferences and provide instantaneous overvoltage protection. Optical couplers are used for some input/output signals to isolate external signals from the control system. The software employs a combination of median and arithmetic mean methods to eliminate instantaneous signal interference, and various optimization techniques are used to improve system robustness. To prevent signal cross-coupling due to common impedance, the system uses a parallel single-point grounding design, separating analog ground and data ground, converging at only one point. 3. Software Design of the Test Device The measurement and control software is written in PL/M196 and compiled and debugged using WAVE6000. The software flowchart is shown in Figure 5. The measurement and control software mainly includes two branches: a signal testing branch and a parameter loading branch. The decision of each branch is based on a voltage signal provided by the ground for testing. If the binding parameter voltage exceeds a given value, the system enters the binding branch. The microcontroller waits to receive binding data, performs data correctness checks, and stores each data item in several shared Flash ROMs via the I2C interface. If there is no binding voltage, the system enters the test branch. The microcontroller begins testing each signal, packages the test data into frames, calculates the CRC checksum of all data, sends it to the receiving device, and judges the test data to determine the system workflow. Due to the large amount of data and the large number and types of signals to be tested, the data frames to be packaged and sent are over 70 bytes long, sent every 10ms at a baud rate of 115.2k. Excluding measurement, control, and framing time, the data transmission time needs careful calculation. Using polling and standard interrupt testing, 10ms is far from sufficient; oscilloscope measurements show that testing and transmitting one frame of data takes 70ms. This system uses the PTS (Peripheral Event Server) interrupt mode, controlled by a microcode hardware interrupt processor, which consumes very little CPU time, similar to DMA in a PC, without modifying the stack or saving status words. This system adopts the PTS block transmission method. Only the PTS control word, the start address of the data block, and the data length need to be provided. An interrupt mask register needs to be defined, and finally, PTS interrupts and standard interrupts need to be enabled. Thus, the testing and transmission of one frame of data takes 6.5ms. Test experiments show that using a microcontroller, PSD, CPLD, and voltage conditioning circuit as the main components to complete the acquisition and control of SCS-related information is not only highly efficient and feasible, but also an effective way to miniaturize and intelligentize the SCS testing device and improve the reliability of the testing system. Microcontrollers and programmable logic devices (PLDs) are highly complementary. Microcontrollers have a high performance-to-price ratio, flexible functions, easy human-machine interaction, and good data processing capabilities. Programmable devices such as CPLDs and PSDs have advantages such as high speed, high reliability, convenient and standardized development, and easy maintenance. This circuit structure of a microcontroller plus an external programmable device has broad application prospects in many high-performance instruments and electronic products.