Autonomous Driving Classification Standards: The Foundation for Understanding Differences in Chip Requirements
Currently, the internationally widely adopted standards for classifying autonomous driving mainly include the SAE J3016 Recommended Practices published by the Society of Automotive Engineers (SAE) in 2014: Classification and Definition of Terms Related to Driving Automation Systems for Road Motor Vehicles, and the national standard GB/T 40429-2021 for Classification of Driving Automation for Automobiles issued by the State Administration for Market Regulation of my country in 2021.
The SAE standard classifies autonomous driving into six levels, from L0 to L5. Level L0 is no automation, relying entirely on manual driving; Level L1 is driver support, primarily relying on manual control, with the system only providing timely assistance such as anti-lock braking systems and electronic stability programs; Level L2 achieves partial automation, where the autonomous driving system can complete certain driving tasks, but the driver still needs to constantly monitor road conditions and be ready to correct system errors; common systems like adaptive cruise control and active lane keeping systems fall into this category; Level L3 achieves conditional automation, where the vehicle's autonomous driving system has higher priority than the driver in specific scenarios, although the driver can regain control via an emergency button, such as the Audi A8's automatic following function in congested traffic; Level L4 enters a highly automated stage, where the vehicle can autonomously complete all driving operations and handle emergencies in designated roads and environments, allowing the driver to even do other things inside the car; Level L5 is fully automated, capable of completing driving tasks under any road and condition, at which point the concept of a cockpit may no longer exist.
In my country, the standard refers to Levels L1 and L2 as assisted driving and Levels L3 and L5 as autonomous driving. Different levels of autonomous driving have vastly different requirements for chip performance, functionality, and reliability, which has driven continuous innovation in autonomous driving chips.
Level 1-2 Autonomous Driving Chips: From Simple Assistance to Basic Intelligence
At Level 1, autonomous driving chips primarily focus on processing limited sensor data to achieve basic driver assistance functions. For example, Adaptive Cruise Control (ACC) requires the chip to process distance and speed information of vehicles ahead from radar, while Lane Keeping Assist (LKA) relies on the chip to analyze lane line images captured by cameras. At this stage, the chip typically has lower computing power and relatively low power consumption, sufficient for simple sensor data processing and basic algorithm execution. For instance, Mobileye's early EyeQ3 chip for Level 1-2 vision-based ADAS had a computing power of only 0.256 TOPS, yet it adequately supported the functions required at this level.
With technological advancements, Level 2 autonomous driving systems offer richer functionalities, such as automatic lane changing and automatic parking. This necessitates chips with greater computing power and more complex algorithm processing capabilities. To handle multi-sensor data fusion and more complex environmental perception tasks, Level 2 chips are beginning to employ multi-core processors and high-performance graphics processing units (GPUs). For example, NVIDIA's Xavier chip, launched for the Level 2 market, boasts a computing power of 30 TOPS and has been successfully applied in models such as the XPeng P7/P5. Furthermore, chips at this stage also face challenges in power management, requiring improvements in performance while ensuring that the overall energy efficiency of the vehicle is not significantly impacted.
Level 3 Autonomous Driving Chip: A Key Step Towards High Intelligence
Level 3 autonomous driving systems place higher demands on environmental perception and decision-making capabilities. In certain scenarios, the vehicle must be able to make fully autonomous decisions and drive, although the driver still needs to maintain a certain level of attention and be able to take over the vehicle at any time. To achieve this, Level 3 autonomous driving chips need to integrate more types of sensors, such as LiDAR and infrared sensors, to obtain more comprehensive and accurate environmental information.
In terms of algorithms and decision-making logic, chips must possess more advanced processing capabilities. Taking the Level 3 autonomous driving system in the Audi A8 as an example, the chip behind it must collaboratively process data from 24 sensors and 41 types of driver assistance system software. At this point, the chip's computing power requirements increase significantly, typically exceeding 100 TOPS. Simultaneously, to ensure safe and reliable operation in complex traffic scenarios, the chip's functional safety and reliability design have reached new heights, needing to meet more stringent automotive-grade standards to cope with various potential risks and failure scenarios.
Level 4-5 Autonomous Driving Chips: Super Brains Pushing the Limits
Level 4 autonomous driving requires vehicles to drive fully autonomously in specific environments without driver intervention, which means chips need to possess powerful computing and decision-making capabilities. These chips typically employ dedicated deep learning chips and artificial intelligence processors to handle the real-time processing of massive amounts of data and accurate judgments in complex scenarios. For example, NVIDIA's Atlan chip, designed for Level 4-5 autonomous driving, boasts a computing power of up to 1000 TOPS and is expected to enter mass production in 2025. This chip needs to process complex data fused from multiple cameras, LiDAR, millimeter-wave radar, and other sensors, using deep learning algorithms to accurately model and predict the surrounding environment, thereby making optimal driving decisions.
Level 5 autonomous driving chips push the limits even further, aiming for fully autonomous driving under any conditions. They not only require extremely high computing power, potentially reaching thousands of TOPS, but also highly integrated multi-sensor fusion technology to ensure timely and accurate responses to various complex road conditions and environmental changes. Simultaneously, the chip's intelligent algorithms and decision-making logic must reach near-human or even surpass human levels to cope with extreme conditions such as extreme weather and unexpected road incidents. Furthermore, Level 5 chips must be absolutely reliable, as any malfunction could lead to serious safety incidents.
Technological Changes in the Evolution of Autonomous Driving Chips
exponential growth in computing power
From Level 1 to Level 5, the computing power requirements for autonomous driving chips are showing an exponential growth trend. The computing power requirements for Level 1-2 may only be a few to tens of TOPS, but for Level 4-5, the requirements skyrocket to hundreds or even thousands of TOPS. This growth stems from the need to support complex environmental perception, multi-sensor data fusion, and advanced decision-making algorithms. To achieve high computing power, chip manufacturers are constantly adopting advanced manufacturing processes, such as evolving from the early 28nm to 16nm, 7nm, and even more advanced processes, to integrate more transistors within a limited chip area and improve computing power.
Continuous optimization of architecture
Early autonomous driving chip architectures were relatively simple. However, with increasing functional complexity and computing power demands, heterogeneous multi-core SoC processor architectures have become mainstream. This architecture integrates multiple modules such as CPU, AI chip (GPU/FPGA/ASIC), and deep learning acceleration unit (NPU). Each module performs its specific function: the CPU handles routine task processing, the GPU excels at parallel computing to process image and video data, and the NPU focuses on accelerating deep learning algorithms. For example, Black Sesame Technologies' Huashan-2 (A1000) chip uses a 16nm process, boasts a powerful computing power of 40-70 TOPS, power consumption of less than 8W, and excellent computing power utilization. Its multi-core heterogeneous architecture enables it to efficiently handle various tasks in autonomous driving.
Functional safety and reliability improvement
As the level of autonomous driving increases, the requirements for the functional safety and reliability of chips in vehicles become increasingly stringent. At Level 3 and above, a chip failure can have serious consequences. Therefore, automotive-grade chips adhere to strict standards such as AEC-Q100 during the design and manufacturing process, employing redundancy design, fault detection, and fault tolerance mechanisms to ensure stable and reliable operation in various complex environments. For example, ChipEngine Technology's "Star One" (AD1000) uses a 7nm automotive-grade process, complies with the AEC-Q100 standard, and incorporates an ASIL-D functional safety island, fully meeting the needs of Level 2 to Level 4 autonomous driving.
Enhanced multi-sensor fusion processing capabilities
Starting with Level 2, autonomous driving systems gradually incorporate various sensors, such as cameras and radar, to achieve more accurate environmental perception. Levels 3-5 rely even more heavily on multi-sensor fusion. Autonomous driving chips need powerful multi-sensor fusion processing capabilities to efficiently fuse and analyze data from different types and levels of precision, eliminating data conflicts and redundancy, and providing accurate information for vehicle decisions. This requires continuous optimization of chip interface design and data processing algorithms to adapt to the demands of multiple sensor access and high-speed data transmission and processing.
Summary and Outlook
From L1 to L5, autonomous driving chips have undergone significant changes in computing power, architecture, functional safety, and multi-sensor fusion processing to adapt to the evolution of autonomous driving technology from simple assistance to fully autonomous driving. Currently, although significant progress has been made in the L2-L2+ level autonomous driving field, becoming an important selling point for automakers and a focus of market competition, moving towards L4-L5 level fully autonomous driving still faces many challenges, such as the development of ultra-high computing power chips, the optimization of complex algorithms, further improvement of functional safety and reliability, and effective cost control.
In the future, with continuous breakthroughs in semiconductor technology, ongoing innovation in artificial intelligence algorithms, and the deep integration of the automotive and technology industries, autonomous driving chips are expected to undergo even more significant changes. On the one hand, we anticipate the emergence of chips with stronger computing power, lower power consumption, and lower costs, driving the large-scale popularization of autonomous driving technology. On the other hand, with the deep integration of chips and vehicle systems and the trend of software-defined vehicles, autonomous driving chips will play a more central role in the entire automotive ecosystem, accelerating the arrival of the intelligent vehicle era and bringing people a safer, more efficient, and more convenient travel experience.
