I. Flow Sharing Control Principle and Topology Selection
The core of parallel current sharing is to force the output current of each module to be consistent through a feedback mechanism. Common topologies include:
Master-slave control method: One module is designated as the master module (voltage control), and the rest are slave modules (current following). In a communication power supply case, the master module's output voltage is set to 48V±0.1V, and the slave modules achieve current following by sampling the master module's voltage, with a current sharing error of <3%. However, a failure of the master module will cause the system to crash, requiring redundant design.
Automatic current sharing method: The current signal of each module is averaged through the current sharing bus, and used as feedback to correct the output voltage. A server power supply test showed that when using the UC3902 current sharing chip, the current sharing error of 4 modules in parallel decreased from 15% to 2.5%, and the failure of a single module did not affect the system operation.
Automatic current sharing method based on maximum current: The module with the highest current is used as the benchmark, and the output voltage of the remaining modules is adjusted to follow. This scheme was adopted in a certain electric vehicle charging station, achieving dynamic current sharing across 6 modules, with a current sharing error of <1% under light load and <5% under heavy load.
II. Key Circuit Design Techniques
1. Current sampling circuit
Sampling accuracy directly affects current sharing performance. We recommend using a Hall effect sensor (such as the ACS712) or a precision resistor + operational amplifier solution.
Hall effect sensors offer good isolation but have relatively low bandwidth (typically <200kHz). In a medical power supply test, the ACS712 exhibited a linearity error of <0.5% at 50A current, meeting the IEC 60601-1 standard.
Precision resistors + op-amps: low cost, but common-mode rejection ratio (CMRR) needs to be considered. An industrial power supply uses 0.1mΩ constantan wire + INA240 op-amps, with a sampling error of <0.2% at 100A current, but RC filtering is needed to suppress switching noise.
2. Current sharing busbar design
The current sharing busbar must have anti-interference capability:
Resistance matching: The bus connection resistors must be consistent (error <1%). A certain communication power supply uses 0.1Ω resistors with 0.1% accuracy, and the measured current sharing error is reduced by 40%.
Filtering capacitor: A 10nF ceramic capacitor connected in parallel at the bus node can suppress high-frequency noise. A test showed that after adding the capacitor, the current-sharing bus ripple decreased from 50mV to 5mV.
3. Compensation Network Design
The current sharing loop needs to be compensated in conjunction with the voltage loop:
Phase margin: Ensure the current sharing loop phase margin > 45° using Bode plot. A 60W power supply with Type III compensation has a measured loop bandwidth of 10kHz, a phase margin of 52°, and a current sharing dynamic response time < 50μs.
Crossover frequency: The crossover frequency of the current sharing loop should be lower than that of the voltage loop to avoid coupled oscillations. In one case, the voltage loop crossover frequency was set to 5kHz, and the current sharing loop crossover frequency was set to 2kHz, and the system operated stably.
III. Debugging Techniques and Troubleshooting
1. Step-by-step debugging method
Single module verification: First, debug the voltage control loop of a single module to ensure that the output voltage accuracy is within ±0.5%.
Two modules in parallel: Gradually increase the number of modules in parallel and observe the change in current sharing error. A test showed that when expanding from 2 modules to 4 modules, the current sharing error increased from 2% to 5%, requiring optimization of compensation parameters.
Dynamic load test: Apply a 10%-90% load step and observe the current sharing recovery time. A certain electric vehicle power supply exhibits a current sharing recovery time of <100μs under a 50A step, meeting the ISO 16750 standard.
2. Troubleshooting
Current sharing bus oscillation: Check the compensation network parameters and increase the damping resistor (e.g., 10Ω). In one case, after adding damping, the oscillation frequency of the current sharing bus decreased from 50kHz to 10kHz, and the amplitude decreased by 80%.
Inter-module current reverse flow: Add a Schottky diode (such as MBR2045CT) to the output terminal to prevent the faulty module from supplying power in reverse. A test of a communication power supply showed that after adding the diode, the reverse current decreased from 3A to <0.1A.
Low-temperature start-up failure: The NTC thermistor failed to cool, causing current limiting to malfunction. A certain medical power supply solved the low-temperature start-up problem by adding a temperature sensor to prevent restarting when the NTC temperature is below 40°C.
IV. Engineering Application Cases
In the upgrade of a 48V/200A communication power supply, the original solution used master-slave control, but the failure rate of the master module was as high as 15%. The problem was solved through the following optimizations:
Instead, an automatic current sharing method based on average current was adopted, using the UC3902 chip to achieve dynamic current sharing.
The current sharing bus layout was optimized, reducing the connection resistance from 0.5Ω to 0.1Ω;
Adding a loop compensation network increases the phase margin from 35° to 50°.
Actual measurements after the modification showed that the current sharing error of the 4 modules in parallel was less than 2%, the system MTBF increased from 5,000 hours to 20,000 hours, and the annual failure rate decreased from 8% to 0.5%.
V. Conclusion
Parallel current sharing control of power modules requires careful consideration of circuit design, parameter matching, and dynamic debugging. By appropriately selecting the topology, optimizing the sampling and compensation networks, and employing a step-by-step debugging method, reliable operation with a current sharing error of <5% can be achieved. In the future, with the widespread adoption of SiC/GaN devices, high-frequency power supplies will place even higher demands on the response speed of current sharing control, necessitating further research into digital current sharing and adaptive compensation technologies.
