1. Introduction In 1987, the VME bus was approved as the international standard IEEE 1014-1987. The VME bus system adopts a master/target architecture and asynchronous non-multiplexed transmission mode, supporting 16-bit, 24-bit, and 32-bit addressing and 8-bit, 16-bit, 24-bit, and 32-bit data transmission, with a maximum bus speed of 40 MB/s. The new standard VME64 (ANSI/VI-TA1-1994) in 1996 increased the bus data width to 64 bits, with a maximum data transmission speed of 80 MB/s. The VME64x bus specification, developed by FORCE COMPUTERS, further increased the bus speed to 320 MB/s. Historically, the VME bus has been the preferred choice for real-time embedded systems due to its numerous functions, strong compatibility, parallelism, and high reliability, primarily used in image processing, military communications, radar signal processing, and many other fields. This paper, based on the needs of real-time radar signal processing, uses an FPGA to implement the interface design for communication between a multi-DSP signal processing template local bus and a computer based on the standard VME bus. 2. Functional Characteristics of the VME Bus The functional structure of the VME bus system can be divided into four categories: Data Transfer Bus (DTB), DTB Arbitration Bus, Priority Interrupt Bus, and Utility Bus. Each category includes a bus and its associated functional modules, which together perform a specific function. 2.1 Data Transfer Bus DTB signal lines can be divided into three categories: addressing lines, data lines, and control lines. To accommodate the flexibility of processor addressing and protect the address space, the VME bus provides six address modification lines. Selecting different address modification codes enables 16, 24, and 32-bit addressing changes and assigns specific protection permissions to the address space. Different combinations of control lines and address lines can flexibly control the data transmission width and method, such as 8, 16, 24, and 32 bits. Relying on the interlocking logic of these control signals, the VME bus performs heterogeneous transmission without clock synchronization, thus reliably enabling data transmission between different devices. When the master and slave modules exchange data, the address lines are driven by the master module for addressing. Depending on the number of address lines used, the address can be a short address, a standard address, or an extended address. The number of address lines used is specified by the address modification lines AM0 to AM5. Data lines D00 to D31 are used to transmit 1 to 4 bytes of data. The master module uses data strobe lines DS0 to DS1, word length line LWORD, and address line A01 to define different data transmission cycle types. The truth tables for data length selection and address bus are shown in Tables 1 and 2. 64-bit data and address buses are not discussed here. 2.2 DTB Arbitration Bus In the VME bus system, when multiple modules simultaneously request to use DTB, the arbitration subsystem detects these requests and allows only one module to use DTB at any given time. The arbitration bus consists of 6 bus signal lines and 4 daisy-chain signal lines: bus request lines BR0~BR3; bus busy line BBSY; bus clear line BCLR; bus enable input lines BG0IN~BG3IN; and bus enable output lines BG0OUT~BG3OUT. The daisy-chain signal lines consist of the bus enable input line (BgxIN) and the bus enable output line (BgxOUT) for each board. A daisy-chain signal line from slot n, such as BGxOUT, connects to the BgxIN of slot n+1 on the next board. Slot 1's BgxIN is generally driven by the bus arbitration module of slot 1. In the VME bus arbitration system, there are four priority levels from 0 to 3, with priority 3 being the highest and priority 0 the lowest. This means that the DTB arbitration bus has 4 lines each for bus request, bus enable input, and bus enable output. Each request module drives only one request line and accepts arbitration of the same level of bus enable link; that is, only when x in BRx, BGxIN, and BGxOUT are the same can a first-level arbitration link be formed. As for the arbitration driver module's handling of the four arbitration links, three different methods can be adopted: priority method, round-robin method, and single-level method. Priority arbitration allocates the bus according to a fixed priority order of the four bus requests, from the highest BR3 to the lowest BR0. Round-robin arbitration allocates the bus according to the principle of round-robin priority; if a requesting module on a bus request line BR(n) has been granted access to the bus, then the highest priority for the next arbitration is BR(n-1). Single-level arbitration only accepts requests on BR3 and relies on the daisy chain allowed on BR3 for arbitration. 2.3 Priority Interrupt Bus Typically, only one processor handles interrupts, monitoring the interrupt request lines (IRQ1~IRQ7), with IRQ7 having the highest priority. When responding to an interrupt, an address cycle is generated, indicating that the request has been responded to. The interrupt response line (IACK) is changed by the arbitrator and transmitted downwards in a daisy-chain manner using IACKIN and IACKOUT signals. A data cycle identifies the requesting device and extracts the status and IV (interrupt vector) of the requesting device. 2.4 Practical Bus The practical bus provides system cycle timing, power-on initialization, and fault detection functions. It mainly includes SYSCLK (system clock line), ACFAIL (AC fault line), SYSRESET (system reset line), and SYSFAIL (system fault line). The system clock line is an independent 16 MHz clock signal generated by the system clock driver module located in slot 1, serving as the time base for the entire system. The other three signal lines are generated by the power monitoring module in slot 1. 3 System Interface Design Scheme Typically, designing the interface between a multi-DSP local bus and a standard bus can utilize interface control chips provided by specialized companies. For example, the Cypress VIC64 bridge circuit can be used to design a fully functional standard VME bus interface with complete master/slave module capabilities. However, if the user-developed VME bus-based application module only acts as a slave device, then only a slave-slave module bus interface is needed. In this case, the FPGA can be used to design the bridge circuit. This design, based on system requirements, uses dual-port RAM for data exchange and the FPGA to implement interface logic conversion. The interface design scheme is shown in Figure 1. In Figure 1, the DSP is an Analog Devices TS101, and four TS101 chips share a bus to form a tightly coupled system. The dual-port RAM is a Cypress CY7C025AV, a high-speed, high-capacity, low-power chip with a capacity of 32 kB, a data width of 16 bits, and a maximum access speed of 80 MHz. The FPGA is an Altera EPF10K30A. The left port of the dual-port RAM is connected to the local bus of the multi-DSP. The MS0 of the local bus is connected to the CEL (left port enable) of the dual-port RAM. The address space of the dual-port RAM in the multi-DSP local bus is mapped to 0x8000000～0x8007FFF. The read/write timing of the dual-port RAM is the same as that of ordinary memory, and it can be directly connected to the local bus. The DSP can access the address space of the dual-port RAM through a slow bus transfer protocol. The OEL (left port output enable) and RWL (left port read/write enable) of the dual-port RAM are connected to the RD and W/R of the local bus, respectively. The left port data lines (D0L~D15L) and address lines (A0L~A14L) are also connected to the local bus data and address lines, respectively. The right port of the dual-port RAM communicates with the standard VME bus. The FPGA is responsible for decoding the standard VME bus control signal lines to generate the interface control logic. The right port data lines (D0R~D15R) and address lines (A0R~A14R) of the dual-port RAM are connected to the standard VME bus data and address lines after being driven by the bus driver 74F16245. The enable and transmission direction signals of the 74F16245 are generated by the FPGA. The standard VME bus control signal lines are connected to the FPGA. Since the FPGA's I/O pins are compatible with various voltage levels, the VME control signal lines can be directly connected to the FPGA. 4. FPGA Interface Program Design The VME bus interface program in the FPGA mainly consists of two modules. One module is the general I/O module for VME host access to dual-port RAM. This module mainly implements the logic conversion from standard VME bus access timing to dual-port RAM access timing, VME bus address decoding and access mode decoding, and the logic control of the data address line drive from the VME bus to the dual-port RAM. The other module is the interrupt request module for multiple DSP modules to send interrupts to the VME host. This module mainly completes the transmission of interrupt signals, the processing of interrupt recognition from the host, and the transmission of interrupt status and identification code to the host. 4.1 Design of General I/O Module The general I/O module program is implemented using a VHDL state machine. The entire process is divided into five states: idle, selection, write, read, and answer. The idle state indicates that this module is not being accessed by the VME host; the selection state indicates that the address and mode decoding has selected this module, and the host wants to access the address space of the dual-port RAM; the write state indicates that the VME host is writing data to the dual-port RAM; the read state indicates that the VME host is reading data from the dual-port RAM; and the answer state indicates that this module responds to the access cycle by sending a data transmission response to the VME host. The state transition diagram describing the entire process is shown in Figure 2. The standard transmission process of the I/O module is described as follows: In the idle state, the address monitoring module should be in the VME bus address decoding and access mode monitoring state, and the access mode of this module is the A24-D16 standard data access mode. When the address and access mode output by the VME host are consistent with this module, that is, the input addresses VA20~VA23 are the addresses set by the program, the AM code is equal to 3A(H), LWORD is high, VA1 is low and AS is low, the address monitoring module outputs a "slave module selected signal", starting slave module access, and the module enters the selection state. After entering the selection state, the program monitors DS0, DS1 (data strobe signals) and WRITE (read/write signal). When DS0 and DS1 are both low and WRITE is high, the module enters the read state; when DS0 and DS1 are both low and WRITE is low, the module enters the write state. When the module is in the read state, the FPGA sets the dual-port RAM's CER to low to enable the dual-port RAM, OER to low to enable data output, and RWR to high to disable write enable, making the dual-port RAM a data output state. The FPGA also needs to enable the bus driver, set the bus drive direction, and make the VME address bus an input and the data bus an output. When the module is in the write state, the FPGA sets the dual-port RAM's CER to low to enable the dual-port RAM, RWR to low to enable the write signal, and OER to high to disable output data enable, making the dual-port RAM a data input state. The FPGA also needs to enable the bus driver, set the bus drive direction, and make both the VME address and data lines inputs. To enable "read acknowledge" and "write acknowledge," the module enables a counter after entering either the read (read data state) or write (write data state). When the counter reaches a certain value (this value can be used to adjust the read/write cycle size; in this example, a count of 1 is sufficient when using a 32 MHz clock), both "read acknowledge" and "write acknowledge" are enabled, and the module enters the answer state. After the module enters the answer state, the program sets DTACK low and sends a data transmission acknowledgement to the host. Thus, when the host writes data to the dual-port RAM, it notifies the host that the bus can be released; when the host reads data from the dual-port RAM, it notifies the host that the data is stable and can be latched. Upon receiving DTACK, the host releases DS0, sets DS1 high, and AS high; the module detects that DS0, DS1, and AS are high, sets DTACK high, disables the dual-port RAM enable and VME bus driver, and the module enters the idle state, ending a standard VME bus transmission cycle. The simulation timing waveforms for the entire process are shown in Figure 3. In the figure, "000" represents the idle state, "001" represents the selection state, "101" represents the read state, "011" represents the write state, and "111" represents the answer state. 4.2 Design of the Interrupt Request Module This module is designed using VHDL language. The function of the interrupt generation module is described using processes, specifically using if-elsif-else statements within a process to describe the timing process. The interrupt module is responsible for generating standard VME bus interrupts and handling interrupt responses sent by the VME host interrupt management module. The program designs an 8-bit internal register VINT to control the generation of interrupt signals. Register bits VINT1-7 correspond to IRQ1-7, controlling the generation and cancellation of VME bus interrupt signals. VINT0 serves as the interrupt enable bit. When VINT0 equals 1, the program checks VINT1-7, sets the corresponding interrupt request signal lines IRQ1-7 low, and sends an interrupt request to the VME host interrupt management module monitoring the signal. After the interrupt request module sends an interrupt request, it monitors the input signals IACK-IN and A1~3, waiting for the interrupt response from the VME host interrupt management module. When IACK-IN is detected to be low, it starts the interrupt number comparison, checking whether the values ​​on A1~3 match the interrupt number sent by this module. If they do not match, it drives the IACKOUT output daisy chain to low. If they match, it puts the interrupt status/identification code on VD0~7. When the data stabilizes, it drives DTACK to low, notifying the VME host interrupt management module to retrieve the interrupt status identification code, and the host enters the corresponding interrupt service routine. This completes the process of sending and responding to the interrupt from the module's VME bus. 5 Conclusion The design of the multi-DSP local bus to standard VME bus general I/O module and interrupt request module was implemented using VHDL language. The dual-port RAM storage space is mapped to the industrial control computer's storage space at addresses 0XC0410000~0XC0413FFFC. Using a 32 MHz clock, the communication rate can reach 16 MB/s, which can meet the requirements of communication between the radar signal processing board and the terminal.