The PCI (Peripheral Component Interconnect) bus is one of the most popular industrial control buses today. It is widely used in computers, and due to the strong support from numerous manufacturers, many solutions in embedded devices now include the PCI bus. In multi-master PCI system applications, arbitration authorization signals must be provided for each master device. Many manufacturers have released dedicated chips with PCI arbitration logic or chips that integrate PCI arbitration logic, but their use is not flexible enough. To make PCI devices easier to use in embedded systems, this paper introduces a design method for a PCI bus arbitrator based on a CPLD (Complex Programmable Logic Device). This method can tailor a PCI bus arbitrator to the specific system requirements, without being limited by the requirements of a specific chip, and has good application prospects in terms of size, functionality, cost, and many other aspects. 1 Introduction to PCI Bus Arbitration 1.1 Arbitration Principle of the PCI Bus The PCI bus is a shared bus that can connect multiple master devices, but due to the exclusive nature of data transmission, only one master device can occupy the bus at any given time. Therefore, in order to effectively utilize the PCI bus bandwidth, a bus arbitrator must be set up to coordinate the operation of each master device in the system according to a certain algorithm. Each PCI device with master device function must provide two arbitration-related signals: REQ# and GNT#. Among them, REQ is a request bus signal, issued by the device that needs to initiate a PCI transmission transaction; GNT# is a bus authorization signal, issued by the PCI bus arbitrator after adjudication. The PCI device that receives the GNT# signal will start operation after the next bus idle. The PCI bus arbitration adjudication process can be completed during PCI transmission without occupying the PCI bus bandwidth, which is called implicit arbitration. That is, the device that needs to initiate PCI operation can issue a request REQ at any time, and the PCI arbitrator will immediately approve the request and issue GNT. However, the actual transmission operation must wait until the current transmission is completed, that is, after the bus is idle. Figure 1 illustrates the relationship between PCI bus devices and the arbitrator. 1.2 PCI bus arbitration rules (1) The arbitration algorithm of the arbitrator must ensure that all devices have the opportunity to be authorized, otherwise there will be a situation where a low-priority device can never occupy the bus to perform transaction operations. (2) If the FRAME is invalid, the GNT can be withdrawn at any time to serve another master device or as a response to the master device withdrawing the REQ. (3) If the GNT signal is withdrawn but the FRAME is signaled and the bus is currently transmitting data, the operation is legal. (4) If the bus is not idle, the withdrawal of one GNT and the issuance of another GNT are allowed to occur in the same cycle. If it is idle, there must be a clock cycle interval between the withdrawal of one GNT and the issuance of the next GNT, otherwise there may be conflicts on the AD and PAR lines. (5) Each issuance of the GNT signal is limited to the corresponding bus master device using the bus for one bus operation (from the issuance to the withdrawal of one FRAME). If the master device needs multiple bus accesses, it can keep the REQ signal valid. The arbitrator will decide whether to award the master device according to a specific arbitration algorithm. (6) A master device can withdraw its REQ signal at any time. Once the REQ signal is withdrawn, the arbitrator will consider that the device no longer requests to use the bus and thus withdraw its GNT signal (see (1) above). If a master controller only wants to perform one bus transfer, it should cancel REQ in the same clock cycle as issuing FRAME. (7) If the current master controller has not started bus operation for 16 idle cycles after issuing its GNT signal, the arbitrator considers it to have timed out. The arbitrator can cancel the GNT signal at any time to serve another device. 1.3 PCI Bus Arbitration Algorithm Currently, the algorithms used for PCI bus arbitration are mainly fixed priority algorithm and dynamic priority algorithm. In the fixed priority algorithm, the priority of each device is predetermined, and the arbitrator allocates the right to use each device according to the predetermined priority. The disadvantage of this algorithm is that once the PCI bus is very busy, the high-priority device will occupy the bus and will cause the low-priority device to be unable to request the bus. It can be seen that this is an unfair algorithm and is only suitable for situations where the bus utilization rate is very low. The dynamic priority algorithm dynamically changes the priority of each device after each arbitration authorization. Under the condition that each device has a chance to obtain the bus, the priority change algorithm can be of various kinds. The most commonly used is the cyclic priority algorithm, that is, the priority of the device in the queue is increased by 1 after each arbitration authorization. Because of its simple algorithm and effectiveness in most applications, this design adopts the cyclic priority algorithm. 1.4 Bus Docking When the PCI bus is idle, it takes at least 2 clock cycles for a device to request bus access and be authorized to use it, which is a waste of the PCI bus. Therefore, the arbitrator usually selects the device that most frequently occupies the bus and assigns GNT# to it when the PCI bus is idle. This is called bus docking. When the bus is idle, the device can be immediately approved to occupy the bus. 2 Implementation of a Dual-Master PCI Bus Arbitrator The following describes the hardware implementation of a bus arbitrator with two devices: a TriMedia embedded DSP CPU PNX1300 and an Intel i82559 network controller. The system structure is shown in Figure 2. For design convenience, three types of state machines are designed in the program: bus state machine, bus master device query state machine, and arbitration state machine. 2.1 Bus State Machine The bus state machine is used to record the state of bus transactions. It is defined as follows: type bus_state is (IDLE, BUSY, LAST_DATA, FINISH) The four states represent bus idle, busy, last data transmission period, and transmission completion, respectively. The state diagram is shown in Figure 3. The following is the state transition relationship of the state machine implemented in VHDL code. 2.2 Bus Master Query State Machine The bus master query state machine is used to determine whether a new master device needs to be assigned. The conditions for reassigning a master device are: (1) the currently authorized device has started transmission; (2) the currently authorized device has not started transmission and timed out. The master device query state is divided into five states: IDLE, GNT1, GNT2, WAIT_NOBUSY, and WAIT_BUSY2, and a counter count is set. When a device on the bus is authorized, but has not started operation after 16 cycles, the count exceeds 16, which is considered a timeout. The arbitrator can revoke its arbitration authorization and transfer it to other devices. The program decides whether to change the arbitration state machine based on the output of this state machine. The state transition is shown in Figure 4. The VHDL code describing the state machine is omitted. The driving conditions of this state machine consist of the output of the bus state machine (busbusy), the state of the arbitration state machine (idle, park), and the timeout signal generated by the counter. The purpose of setting WAIT_BUSY2 is to avoid potential conflicts on the AD and PAR lines. The output of this state machine, search_master, serves as the state transition enable signal for the arbitration state machine. Only when this signal is valid will the arbitration state machine change its current state. 2.3 Arbitration State Machine The arbitration state machine represents the state of the bus arbiter, defined as follows: type arbiter_state is (IDLE, DEV1, DEV2, PARK); When the master device queries the state machine output enable signal (search_master), it causes the state of the arbitration state machine to change. The state transition process is shown in Figure 5. The VHDL code describing the state machine is omitted. The arbiter controls the issuance of the arbitration grant signal (GNT) based on the current state of the arbitration state machine. Note: PARKMASTER is a pre-set docking state. 2.4 Simulation Waveform Diagram As shown in Figure 6, the test file simulates the scenarios of one device request and two devices requesting simultaneously, and provides the bus grant signal (GNT), verifying the correctness of the arbitrator logic. 2.5 Resource Usage Analysis The programmable logic device used is Lattice's ispLSI2064E-135LT100. The example program was synthesized in ispLever, and the results are shown in Table 2. The latency analysis after synthesis shows that the minimum clock cycle of this logic is 7.5ns, meaning that this logic can operate in systems below 133MHz and is fully capable of handling arbitration on a 33MHz PCI bus. This PCI bus arbitrator has been successfully applied in a PNX1300-based IP video conferencing terminal system to handle bus occupancy arbitration between the embedded CPU PNX1300 and the network controller 182559. This video conferencing terminal passed testing at the National Telecommunication Technology Labs (NTTL) in January 2005 and obtained a network access license.