This paper designs a speed capture circuit using a DSP chip and peripheral circuits in the hardware circuit. The motor drive controller uses a microcontroller chip and peripheral circuits to construct circuits for current sampling, overcurrent protection, and pressure regulation. A CPLD is used to implement the logical commutation of the rotor position signal of the brushless DC motor. In terms of software design, the system control is implemented using a combination of C and assembly languages. Finally, a fuzzy control strategy for adjusting PID parameters is proposed. 1 Introduction The racing car braking system is a relatively independent subsystem of the racing car system. Its function is to bear the static weight and dynamic impact load of the racing car, as well as absorb the kinetic energy during braking, thus achieving braking and control. Its performance directly affects the racing car's rapid response, safe braking, and survivability, thereby affecting the overall performance of the racing car. This paper designs the hardware and software of a fully electric anti-slip brake controller for racing cars, and finally studies a control law suitable for racing car braking. 2 System Hardware Circuit Design This racing car brake controller consists of an anti-slip controller and a motor drive controller. Both controllers are based on a DSP chip. The anti-slip controller primarily controls the slip ratio, outputting a given braking pressure. It uses a DSP chip as the CPU, along with signal conditioning circuits for the racing car and wheel speeds. The motor drive controller mainly adjusts the braking pressure and controls the motor current. It also uses a DSP chip as the CPU, along with peripheral circuits such as a motor current feedback conditioning circuit, overcurrent protection circuit, brake pressure conditioning circuit, and four sets of three-phase full-bridge inverter circuits. 2.1 DSP Minimum System The DSP minimum system mainly involves memory expansion, JTAG interface configuration, reset circuit, ADC module settings, and clock circuit design. 1. External Memory Expansion. External memory is used to compensate for the insufficient internal RAM of the DSP, and also to facilitate program downloading to external high-speed static RAM during debugging. The external static random access memory uses a CY7C1041CV33. The DSP can use either on-chip or off-chip program memory, determined by the XMP/MC pin. JTAG Interface. When the program needs debugging, the program download is completed through the JTAG interface, which is connected to the parallel port of the PC via the emulator. 2. Reset Circuit and Clock Source Module. A resistor-capacitor circuit generates a low-level reset signal for power-on reset and manual reset. An external hardware watchdog is added, whose output generates a reset signal WDRST. The power supply chip has two inputs of +5V and outputs of +1.9V and +3.3V to power the DSP. The output power supply has two reset signals; when the power supply is unstable or too low, a reset signal will be generated. 3. Hardware Configuration of the Analog-to-Digital Converter (ADC) Module. The ADC output voltage is 2V, requiring a low-ESR ceramic capacitor (10μF) connected to analog ground at the output. If the software is set to external reference mode, ADCREFP can be connected to an external reference voltage of 2V and a low-ESR capacitor (1μF to 10μF). Otherwise, the accuracy of the ADC's internal reference source will be affected. 2.2 Racing Car Front Wheel and Brake Wheel Speed ​​Signal Processing Circuit The racing car anti-slip controller primarily uses slip ratio as the control object to prevent the car from slipping. It outputs a pressure reference value after adjusting for the deviation in slip ratio to track the given slip ratio. The anti-slip controller must have conditioning circuits for the speed signals of the racing car's front wheel and brake wheel, mainly to obtain the feedback slip ratio. The racing car speed signal is represented by the speed signal of the freely rolling front wheel. Speed ​​sensors are installed on both the front wheel and brake wheel of the racing car. When the wheel rotates, the speed sensor generates a sinusoidal AC signal. For each revolution of the wheel, the speed sensor emits 50 cycles of sinusoidal AC signal. The amplitude of the sinusoidal AC signal varies with the wheel speed. The signal is a sinusoidal signal with a bias voltage of 2.5V, a peak value of 0.3V, and a maximum signal amplitude not exceeding 5V. This sinusoidal signal is converted into a square wave of the same frequency and sent to the capture unit of the DSP. By capturing the count interval ncapture between adjacent rising edges of the square wave, the wheel rotation speed V can be calculated. The speed conditioning circuit is shown in Figure 1: Figure 1 Speed ​​Conditioning Circuit 2.3 Logic Signal Circuit The motor driver uses ALTERA's MAX7000A series devices to process the rotor position and other signals of the motor. The EPM7128AE, with up to 76 programmable I/O ports and 100 pins, is selected. This CPLD meets the system design requirements. The EPM7128AE device implements the motor's three-phase full-bridge inverter circuit trigger signal, overcurrent protection, forward and reverse rotation, and the on/off functions of the three-phase full-bridge. One CPLD device, EPM7128AE, has logic signals for two motors. Since the output of the CS3020 Hall position sensor for the brushless DC motor is an open-collector structure, a 2KΩ resistor is pulled up, and the Hall signals SA, SB, and SC are sent to the input port of the CPLD. The four terminals TMS, TCK, TDI, and TDO of its JTAG interface must be connected to pull-up resistors and then to a +5V power supply. 2.4 Power Drive Circuit of Brushless DC Motor The power drive circuit of the brushless DC motor adopts a three-phase full-bridge inverter circuit composed of six N-channel MOSFETs, centered around the IR2130 dedicated driver chip from IR Systems. Its input is a PWM wave with power ground as the ground, which is sent to the input port of the IR2130. The output controls the N-channel power drive MOSFETs, thereby driving the brushless DC motor. This driving method mainly relies on the clever use of the IR2130 power drive chip's "bootstrapping" technology to create a floating high-voltage side power supply, simplifying the design of the entire drive circuit and improving system reliability. Furthermore, the IR2130 driver chip has built-in dead-time circuitry, as well as overcurrent and undervoltage protection functions, greatly reducing the complexity of circuit design and further improving system reliability. 2.5 Current Sampling and Overcurrent Protection Circuit The current of the brushless DC motor is detected by a resistor on the bus of the power drive circuit. The busbar resistor consists of two 0.01Ω power resistors connected in parallel. The sampling circuit samples the current through these two parallel sampling resistors. The sampling resistors convert the current signal into a voltage signal, which is then sent to the current monitoring chip for amplification. After filtering by a second-order active filter circuit composed of OPA2344, the final current feedback signal is sent directly to the A/D converter. Figure 2 shows the hardware overcurrent protection circuit of the current sampling circuit, which plays a crucial role in the normal operation of the system, primarily protecting the power devices MOSFETs and the motor. The system also has software protection functionality. The overcurrent signal OVCURX is sent to the input pin of the DSP. When OVCURX is high, the DSP generates the motor control rotation signal ENABLE, a logic signal to stop the motor. The IR2130 chip itself has overcurrent protection functionality. 2.6 Pressure Signal Amplification Circuit and its Conditioning Circuit The pressure signal amplifier uses a differential subtraction amplifier circuit, with an ultra-low drift voltage operational amplifier as its core. The amplification factor is 40 times, and the amplifier also features zero-adjustment and sensitivity adjustment functions. Chip 7809 provides +9V to power chip 7660, which then converts the +9V voltage to -9V. Both +9V and -9V power OP07. Since the voltage signal from the voltage signal amplifier ranges from +1V to +5V, while the reference voltage of the DSP's A/D module is +3.3V, the maximum value of the sampled voltage signal cannot exceed +3.3V. Therefore, the voltage signal must be reduced to below +3.3V by a conditioning circuit. The conditioning circuit uses a precision operational amplifier OPA2344 to condition the voltage signal from +1V to +5V to below +3V. The amplification factor needs to be set to 0.6 to facilitate DSP sampling. 3. Controller Software Design The software for this racing car brake controller is primarily written in C language, with appropriate use of assembly language. This approach simplifies the overall system software design. C language accelerates DSP program development and greatly increases readability and portability. Program debugging is performed using TI's C2000 Code Composer Studio (CCS) integrated development environment. Due to space limitations, this section only introduces system program initialization and the main program flow. 1. System Program Initialization. Before running, the system program must initialize the DSP's clock source, timers, watchdog timer, AD module, I/O ports, capture units, interrupts, etc., ensuring that the system's internal resources, peripheral devices, and hardware circuits are compatible. All interrupts must be disabled before system operation to prevent unnecessary interrupts or program crashes. Therefore, interrupts are enabled only after initialization to ensure normal program operation. 2. System Main Program Flow. The main program of the racing car's all-electric braking system includes a program initialization module, timer interrupt service, analog signal timing sampling module, speed signal capture module, slip ratio control module, pressure regulation module, current regulation module, etc. The timer interrupt service routine provides a fixed clock trigger for the current, pressure, and slip ratio modules, using this time as the adjustment benchmark for each module. When the program runs, it first disables the system's global interrupt to complete initialization. Upon receiving a braking command, it enables the global interrupt and enters an infinite loop for program adjustment until the program terminates. The current loop has the shortest adjustment time and the fastest response. Its adjustment time is related to the current signal filtering parameters, DSP sampling speed, CPU clock cycle, and software filtering program, and is generally a few tenths of a millisecond. The pressure adjustment loop's time is set to N times that of the current adjustment loop. The number of adjustments for both the current and pressure loops can be determined by on-site measurement of the adjustment time. The slip ratio adjustment time is even longer. The main program flowchart of the system is shown in Figure 3. Figure 3: Main Program Flowchart 4. System Fuzzy Control Strategy The fuzzy controller is a key component in the application of fuzzy control in control systems. Its main process involves fuzzifying the precise output of the controlled process in the system control loop and using it as the input to the fuzzy controller. Both the input and output of the fuzzy controller are actual precise quantities. Then, fuzzy inference is performed, establishing linguistic fuzzy control rules internally, and judging the fuzzy output based on the input conditions. Finally, the fuzzy quantity is converted back into the actual precise quantity, i.e., defuzzification. The specific design process of the fuzzy controller is shown in Figure 4. Figure 4: Fuzzy Controller Schematic Diagram. Author's Innovation Points: This paper mainly completes the design of a racing car braking control system, primarily focusing on hardware design, software design, and control strategy research. In terms of hardware design, a high-speed DSP chip and CPLD are used, along with their peripheral circuits. The system also includes a drive circuit based on the IR2130, current signal hardware amplification circuit, filtering circuit, and protection circuit, pressure signal amplification and filtering circuit, and processing circuits for racing car speed and wheel speed, etc. In terms of control strategy, fuzzy control is used to adjust the PID parameters. References: [1] Wang Zhiwei, Ma Mingjiang. Theoretical Mechanics [M]. Machinery Industry Press, 2006 (6), P104-105. [2] Li Hualiang. Research and Design of All-Electric Braking Control System for Racing Cars [M]. Xi'an: Northwestern Polytechnical University, 2006 (6). [3] Su Kuifeng, Lü Qiang, Geng Qingfeng, et al. Principles and Development of TMS320F2812 [M]. Beijing: Electronic Industry Press, 2005 (4). [4] Hu Qinggui, Li Chengzong. Implementation Scheme of Automatic Alarm Braking for Automobiles [J]. Microcomputer Information, 2006, 3-2: 212-214