Introduction To meet the future demands of wireless multimedia communication, the International Telecommunication Union (ITU) proposed the concept of third-generation mobile communication as early as 1985. Many renowned telecommunications equipment manufacturers in various countries and regions subsequently put forward more than ten wireless interface proposals. After thorough negotiation and integration, three major standards were finally formed: WCDMA proposed by Europe and Japan, CDMA2000 proposed by the United States, and TD-SCDMA proposed by China. TD-SCDMA is a 3G wireless communication standard proposed by the China Wireless Telecommunications Standardization Organization (CWTS) and approved by the ITU. Before its actual commercial use, comprehensive and in-depth testing and verification of TD-SCDMA's network performance, data transmission and reception in a real wireless environment using testing equipment is necessary. In response to the current situation in China, where the country is vigorously developing the TD-SCDMA third-generation mobile communication (3G) system and is about to build a large-scale 3G network, but lacks the necessary experimental R&D, network construction, and operational testing equipment, and given that traditional international communication test instrument manufacturers have only launched test instruments based on CDMA2000 and WCDMA standards, developing a TD-SCDMA mobile communication network tester with independent intellectual property rights will improve the TD-SCDMA industry chain, form a series of products, and launch them to the market, which will undoubtedly generate huge social and economic benefits. The signaling acquisition card introduced in this article is one of the most important data acquisition cards for core network testing in the TD-SCDMA network tester that we have successfully developed and which is already commercially available at Chongqing Chongqing University of Posts and Telecommunications Communication Technology Co., Ltd. Design and Implementation 1. Signaling Data Acquisition Card Design Concept This card mainly completes the acquisition of SS7 signaling data based on the selected protocol. This card is based on PCI design and its main functions include: physical layer data acquisition and HDLC link control. In the entire system, it mainly completes layer 1 and layer 2 control, requiring high reliability, availability, and scalability. To meet the requirements of high data traffic and ease of use for network testers, we selected the HDLC controller (MindSpeed ​​Bt8474) with built-in standard PCI protocol specifications, the dedicated E1/T1/J1 framer (MindSpeed ​​Bt8370) chip, and Windows 2000 as the basic hardware and software architecture for this card. Each board can achieve 8 receive and 4 transmit, and the software driver is based on the PCI framework, which can meet the requirements of fast data acquisition and has stable performance. 2 Chip Resource Introduction The main chips used in this card are the MindSpeed ​​Multi-Channel Synchronous Network Controller (MUSYCC) Bt8474 with built-in PCI bus specifications and the E1/T1 framer Bt8370. ● PCI Bus Introduction PCI stands for Peripheral Interconnect. The PCI bus is a local bus that is not attached to a specific processor, and PCI-based systems are not affected by processor upgrades. Each typical PCI can support approximately 10 electrical loads. It supports 32-bit or 64-bit bus widths and supports operating frequencies of 33MHz or 66MHz. When operating at 33MHz/32-bit, the theoretical maximum data transfer rate can reach 133MHz/s. It supports parallel bus operation and fully supports PCI bus master devices. It can realize burst transmission in all read and write operations, supports plug and play, and PCI components and drivers can be used on various platforms. ● Introduction to BT8474 BT8474 is a multi-channel synchronous communication controller (MUSYCC) that can support 128 data channels. Each channel can support three protocols: HDLC, SS7, and transparent transmission, depending on the configuration. In data processing, it mainly completes layer 2 (data link layer) processing. BT8474 is a PCI multi-function device, which mainly includes the following parts: (1) A host interface: The host interface consists of four parts: device configuration register, PCI function 0 configuration space, PCI function 1 configuration space, and PCI interface. The host interface mainly provides the interface between BT8474 and PC, and completes the configuration of device registers and the read and write of PCI function area configuration space. (2) 4 serial ports: The serial port also consists of four parts, including the interrupt controller, DMAC, bit-level processor BLP, and receive and transmit ports. The serial port mainly completes the data transmission between the main interface and BT8370, and generates interrupts as needed, and notifies the PC through INTA. (3) 1 expansion bus port (EBUS): The EBUS interface mainly completes the expansion of peripheral devices through the built-in MPU (microprocessor unit). (4) 1 boundary scan port (JTAG). Its functional block diagram is shown in Figure 1 and Figure 2. Figure 1 Functional block diagram of Bt8474 Figure 2 Serial port function design schematic diagram of Bt8474 ● Introduction to Bt8370 The BT8370 is a T1/E1 transceiver framer that supports a line rate of 1.544Mb/s (T1) or 2.048Mb/s (E1) for the transceiver interface. The physical linear interface circuit recovers the analog clock and data from the cable from "+3dB to -43dB". The BT8370 mainly consists of the following parts: (1) Microprocessor interface (MPU): mainly completes the communication control between other devices. (2) Receive/transmit linear interface unit (RLIU/TLIU). (3) Digital transmitter (XMTR). (4) Data receiver (RCVR). (5) Transmit system bus (TSB). (6) Receive system bus (RSB). (7) Clock rate adapter (CLAD). (8) Boundary scan interface (JTAG). Its functional diagram is shown in Figure 3 and Figure 4. Figure 3 Functional block diagram of BT8370 Figure 4 Design principle diagram of BT8370 3 Hardware implementation of signaling acquisition card Figure 5 is the overall design block diagram of the signaling acquisition card. Figure 5 Overall design block diagram of E1 acquisition card The acquisition card collects No. 7 signaling messages (including No. 1 accompanying signaling) from the E1 line to monitor and simulate the entire call process. The PCI interface chip (HDLC controller) is a multi-functional device, including a network controller and a PCI bridge device (EBUS). The network controller controls time slot mapping and configures DMA transfers; the PCI bridge device is used to select and configure the framer, with the framer selection accomplished by a CPLD. Furthermore, the interrupts for the network controller and the PCI bridge device are separate, reported to the PCI controller via INTA and INTB respectively. After the signaling signals are framed by the framer, they are sent to the PC buffer via DMA through the HDLC controller; users can retrieve signaling data from the buffer for analysis using the interface functions provided by the driver. According to the overall design requirements of the TD-SCDMA network test instrument, the No. 7 signaling card, as a board in the PCI slot, collects E1 signals through a high-impedance adapter, performs framing processing on the 8370, and then sends the data to the 8474 via serial port. After message reassembly, the message is sent to the upper-layer software for protocol analysis and processing. The hardware structure of the No. 7 signaling card provides the physical layer and some link layer functions of the network interface, while the software implements the data control of the physical layer and link layer, as well as some application layer functions. This card can simultaneously perform 8-channel monitoring and 4-channel simulation. According to the task objectives, the No. 7 signaling card is mainly composed of the following hardware units: HDLC logic layer Bt8474, PHY physical layer Bt8370, CPLD logic control, high impedance adapter, DB15, transformer, etc. Figure 6 shows the hardware structure of the E1 acquisition card. Figure 6 Hardware structure innovation of the E1 acquisition card The innovation of the author of this paper: (1) In the hardware design of this card, the 8474 with only four serial ports is expanded to realize 8 serial ports by multiplexing time slots and channels. (2) The signaling acquisition card can monitor the establishment, transmission, and stopping of communication links in real time. (3) The signaling sending function of this card can realize service simulation and reduce the design risk of TD-SCDMA network. (4) This card is now being used commercially in the TD-SCDMA network tester of Chongqing Chongyou Dongdian Communication Technology Co., Ltd. Multiple field tests have proven that this signaling acquisition card can be fully applied to TD-SCDMA network testing and has achieved economic benefits of over one million yuan.