Introduction Controller Area Network (CAN) is one of the few fieldbuses currently approved as an international standard. CAN networks can operate in a multi-master mode. It employs non-destructive bus arbitration technology, and its signal transmission and control use a short frame structure, thus possessing strong anti-interference capabilities and low coupling. The communication rate range of CAN networks is 5 kbps/10 km to 1 Mbps/40 m, and the number of driving nodes can reach 110. Its transmission medium can be twisted pair, coaxial cable, or optical fiber, offering great flexibility. Each frame of information has CRC checksum and other error detection measures, resulting in an extremely low data error rate and high reliability. When a serious error occurs in the transmitted information, the node can automatically disconnect from the bus to ensure that other operations on the bus are not affected. Although bus technologies such as PCI and USB have developed rapidly, the ISA (Industry Standard Architecture) bus is still the most widely used in test microcomputers and industrial control computers. The ISA bus has a 16-bit data width, a maximum operating frequency of 8MHz, a data transfer rate of 16MB/s, and 24 address lines, addressing 16MB of address units. Its bus signals are divided into five categories: address lines, data lines, control lines, clock lines, and power lines. To address the timing and logic coordination issues between the CAN controller SJA1000 and the various signal lines of the ISA bus, this paper designs a non-intelligent adapter card based on the CAN bus. This adapter card has been applied in the "CAN bus-based motion control system" developed by this paper and is operating well. The overall structure of the non-intelligent ISA bus CAN adapter card: The address and data buses of the CAN controller SJA1000 are time-multiplexed, and the address signals on the bus can be latched by the falling edge of the ALE signal; the address and data buses on the ISA bus are provided separately and cannot be directly connected to the address and data buses of the SJA1000. This design uses an address decoding circuit to decode the address signal lines, thereby allocating a specific port address for the CAN adapter card. Then, the data signal transmitted through the ISA data bus in the first I/O operation is latched using the data latch function of the 74HC373 chip, so as to serve as the address signal for accessing the registers in the SJA1000 CAN controller. Finally, the read and write operations of the corresponding address registers in the SJA1000 are completed in the second I/O operation. The overall structure of its adapter card is shown in Figure 1. In Figure 1, the address latch 74HC373 can be regarded as the address port of the SJA1000, while the SJA1000 itself can be regarded as the data port of the SJA1000. There is also a reset port for hardware reset of the SJA1000. The base address decoding circuit in the figure uses AEN as the enable signal. Decoding the address signals A2 to A9 can obtain the base address of the adapter card; combining the address signals AO and A1 can obtain the offset address of each port. The communication between SJA1000 and ISA adopts a two-stage I/O operation method: the first time, the address is sent to the address port, and the second time, the data port is accessed. The address and data ports mentioned here refer to SJA1000. The address of the accessed SJA1000 register and the transmitted data can be obtained through the ISA bus data lines. The control port decoding circuit combines the control signals and address signals sent by the CPU according to a certain logical relationship to generate a new set of functional signals as interface control signals. The SJA1000 reset circuit can reset the SAJ1000, specifically using three hardware reset methods: power-on reset, program reset, and button reset. Adapter Card Hardware Design Base Address Decoding Circuit Design Figure 2 shows a specific base address decoding circuit. Generally, depending on system requirements, the address decoding circuit can decode the port address of the ISA address lines and can be represented by AO~A9. The base address decoding circuit decodes A9~A2, which can then be used as the base address of the port on the card. In Figure 2, 74HC688 is an 8-bit comparator; when Pi=Qi (i=0…7), the inverted output of P=Q is low. When AEN on the ISA bus is high, the bus operates in DMA mode; when AEN is low, the CPU has control over the bus. The operation of the non-intelligent adapter card is essentially the CPU's I/O operation process. During this time, AEN is always low and can be used to control the strobe pin G of the 74HC688. Address selection is only allowed during I/O operations. Because DIP switches are used, the user can preset the adapter card's base address. The offset of each port on the card is selected by A1 and A0 and can be controlled by software. In this design, the address port offset is defined as 00, the data port offset as 01, and the reset port offset as 11. Control Signal Generation Circuit The control signal generation circuit of this adapter card is shown in Figure 3. The main function of this circuit is to combine the control lines and address lines sent by the CPU according to a certain logical relationship to generate a new set of functional signal outputs. This signal can be used as an interface control signal to control the operating state of chips such as SJA1000, 74HC373, and 74HC245. Since the output signal of the base address decoding circuit is the inverse of P=Q (active low), the SJA1000 address port offset address is 00H, and the data port offset address is 01H, therefore, according to the control logic, the control signal logic expression of each chip in the adapter card is as follows: During the operation of the adapter card, the logic timing relationship of each chip is as follows: When the 74HC373 outputs valid data, the 74HC245 output is in a high impedance state; when the 74HC373 output is in a high impedance state, and the SJA1000 data is directly transmitted back to the ISA bus, the 74HC245 input and output work normally. Specifically, assuming the CAN base address is 300H and accessing SJA1000 is completed in two I/O operations, the data sent to port 300H for the first time can be latched in the 74HC373 on the trailing edge of the write signal. In this operation, the E pin of the 74HC245 and the LE pin of the 74HC373 are valid, while the OE pin of the 74HC373 is high, and the output of the 74HC373 is in a high-impedance state. When accessing data port 301H for the second time, SJA1000 is selected, and the CPU can then perform read/write operations on the corresponding unit of SJA1000. The specific operation process is divided into two cases: read and write. When the second I/O operation arrives, the SJA1000 latches the data stored in the 74HC373 during the first I/O operation as an address latch on the falling edge of the BALE signal. During this process, the E inverted pin of the 74HC245 is high, and the output is in a high-impedance state; the OE inverted pin of the 74HC373 is low, and the output is active, allowing the address signal to be transmitted to the SJA1000. After the address is latched by the SJA1000, if a read operation is performed, during the active read signal period (low level), the OE inverted pin of the 74HC373 is high, and the 74HC373 output is in a high-impedance state. At this time, the SJA1000 can output the register contents of the selected cell to the data bus and drive it into the CPU via the 74HC245. After the address is latched, if a write operation is performed, the output enable pin of the 74HC373 remains active, allowing data to be written to the corresponding cell of the SJA1000 during the active write signal period. The timing diagrams for the computer to read and write to the CAN controller SJA1000 via the ISA bus are shown in Figures 4 and 5, respectively. Before the SJA1000 can operate normally, a reliable hardware reset via the reset pin is required to correctly read and write the registers in the SJA1000. The minimum duration of the reset level for the SJA1000 is 0.1 μs, while the PC system reset level can last for several microseconds. The system reset signal RESET is high when the system power is on and can be directly used to reset the SJA1000 after passing through an inverter. Figure 6 shows the adapter card's reset circuit, which provides three reset methods for the SJA1000: power-on reset, program reset, and key reset. In Figure 6, A1 and A0, after passing through a 74LS10 NAND gate, generate an offset address of 11 for the reset circuit. This address signal, combined with signals such as IOW inverted and P=Q inverted, can generate a reset signal for the SJA1000 in conjunction with the program design. In program design, simply writing data to the reset port is sufficient to reset the program. A button reset, on the other hand, can be used to directly reset the SJA1000 CAN controller in the event of a communication failure. Software Design of the Adapter Card The key part of the software design is the design of the CAN communication program. The communication program (flowcharts shown in Figures 7, 8, and 9) can be divided into three parts: CAN initialization program, receiving program, and transmitting program. Initialization is a prerequisite for communication and mainly involves setting some registers of the CAN controller. Since the SJA1000 supports interrupt operations, interrupt service routines can be used to complete data reception and transmission, improving system efficiency. In fact, the SJA1000 can only be initialized in reset mode. Initialization mainly includes setting the operating mode, receiving filter mode, receiving mask register and receiving code register, baud rate parameters, and interrupt enable register. After initialization, the SJA1000 can be set to working state for normal communication. The transmitting subroutine is responsible for sending node messages. During transmission, the status register is read and each bit is appropriately evaluated. The data to be transmitted is then combined into a message frame according to a specific format and sent to the SJA1000 transmit buffer. The SJA1000 then initiates transmission. The receive subroutine is responsible for receiving node messages and handling other situations. During message reception, it also handles situations such as bus shutdown, error alarms, and receive overflow. The CAN adapter card can communicate with the computer via interrupts. However, interrupts cannot be directly controlled in the WIN API; they can only be utilized by writing a virtual device driver (VxD) for the CAN adapter card at the operating system level. This requires virtualizing interrupts in the virtual device driver, writing the necessary code in the interrupt event response function, and providing an access interface for the application. It should be noted that the computer accesses the SJA1000 on the CAN adapter card via the ISA bus using two I/O operations: first, sending an address to the address port, and second, accessing the data port. The specific implementation code is as follows: // Write a byte of data (data) to the specified SJA1000 register (addr), with CAN_BASE as the base address void CanIRQ::writeByte(int CAN_BASE, unsigned char addr, unsigned char data) { _outp(CAN_BASE, addr); _outp(CAN_BASE+1, data); } // Read a byte of data (data) from the specified SJA1000 register (addr) unsigned char CanIRQ::ReadByte(int CAN_BASE, unsigned char addr) { unsigned char result; _outp(CAN_BASE, addr); result=_inp(CAN_BASE+1); return result; } In programs that access SJA1000, the above two sub-functions can be called directly. Thus, its transmission program segment code is as follows : Bool CanIRQ::CanTrans(int CAN_BASE, unsigned char *pTransBuf) { status = ReadByte(CAN_BASE, SR); //SR is the address of the status register for (i = 0; i ≤ ...