Introduction With the development of computer science and automatic control technology, vision systems are widely used in industrial inspection, biomedicine, military reconnaissance, and other fields. Embedded vision systems integrate image acquisition, processing, and communication functions into a single camera, thus providing a multifunctional, modular, highly reliable, and easy-to-implement machine vision solution. Simultaneously, vision sensors need to complete the communication tasks of control information and image data through network design; network communication devices are an important component of vision sensors. This paper uses DSP and CPLD as core chips to control image acquisition, processing, and transmission. After processing by the DSP, the acquired images can be transmitted via Ethernet to a microcomputer for further processing, or communicate with other vision systems and automated inspection devices to form a distributed monitoring network. The advantages of this system design are: · Using CMOS as the image sensor to directly acquire digital images, and employing high-speed DSP and CPLD as core chips to control image acquisition and processing, simplifies circuit complexity, improves system integration, and reduces costs. · Fast image preprocessing is performed within the DSP, improving system intelligence. · Image data is transmitted to a networked computer via Ethernet, facilitating image transmission, storage, and communication with other vision sensors to exchange data, forming a vision network. It can communicate with PLCs, robots, and other automated devices. System Design Figure 1 shows the system block diagram. The system sends an acquisition command to the CPLD via the DSP. The CPLD controls the CMOS image sensor to write image data to the FIFO. Simultaneously, the DSP transfers the image to SDRAM via DMA and performs image processing. After processing, the result is transmitted to a microcomputer or other device via Ethernet. Its I/O interface can be expanded to connect to actuators such as PLCs, triggering external actuators to complete image acquisition and processing, achieving the control and detection purpose. Figure 1 System Block Diagram Image Acquisition Process The image acquisition process mainly involves the DSP sending command words to the CPLD (ALTERA MAX II series EPM240), including control commands such as single-frame acquisition and continuous acquisition. The FIFO is reset before each image acquisition to prevent data retention from the previous acquisition process from causing errors in the current acquisition. Figure 2 shows the simulation waveform of the CPLD acquisition program. It can be seen that when acquiring single-frame data, the CPLD achieves image acquisition by controlling the /WE (write enable signal) of the FIFO (CYCY7C4291V of CYPRESS) between two consecutive VSYNC (frame synchronization signals) to be active low. The OV7640's frame time is 33ms (30 frames/s). Operating in black and white mode, each image has 300KB (640×480), or 9.3MByte/s, while the DSP's read speed can reach 66.7Mbyte/s. If a 16-bit bus width FIFO is used, it can reach 133Mbyte/s. In this system, the CPLD counts the image lines. To ensure that the image data does not overflow the FIFO (128KB), a DMA transfer is triggered every 80 lines of image data (DMA is set to external trigger mode). Each image is divided into 6 transfers (a total of 480 lines of data). Figure 2. Simulation waveform of CPLD acquisition program . Ethernet image transmission . The Ethernet design of this system uses the Wiznet W5100 full-featured hardware protocol stack chip. The W5100 has 16K transmit/receive buffers and supports protocols such as TCP, UDP, ICMP, IPv4 ARP, and IGMP. This system uses the TCP/IP protocol to receive commands from the host computer and execute corresponding image acquisition and processing tasks. Wiznet provides complete Socket API functions, which work similarly to the Windows Socket API. The program is very convenient to write in C language under the TI CCS integrated development environment. Figure 3 shows the system software based on asynchronous Socket written in VC. Images are uploaded under different command codes. If command 1 is entered as shown, a single grayscale image without any image processing can be uploaded. Figure 3. Image receiving software with command options. The system software flow is shown in Figure 4. After system initialization, network settings are configured, a command Socket is established, and after a successful Socket connection, the system is in a TCP connection state. Upon receiving a command, an interrupt trigger causes the DSP to read the command word from the W5100, perform corresponding operations based on the command word, and add an image preprocessing program. Then, the command socket is closed, and the data socket is started for data transmission, sending the processed image data to the host computer for more advanced image processing, ultimately obtaining the desired results and data. Figure 4 shows a software flowchart and an example of the image acquisition and processing program. This system can be applied to multiple fields of vision systems. By developing standard software processing modules, such as geometric edge extraction, blob, grayscale histogram, OCV/OCR, simple positioning and searching, users can select the appropriate processing module according to their actual measurement needs. The host computer compiles the corresponding firmware and downloads it to the system, thereby achieving visual detection with specific functions. Currently, the system development can only complete a few specific functions. The following uses the diameter detection of a disk as an example to introduce the system's processing effect. The basic idea of ​​the algorithm is: first, filter the acquired image; then, use an edge detection algorithm to detect the edge of the circle; finally, use a circle detection algorithm to calculate the outer diameter and aperture of the circle. The basic detection process is as follows: Calibration Before detection can be performed, the system must be calibrated. Calibration determines the mapping relationship between an image and the physical world. Therefore, a one-to-one mapping is established between each point in the image and certain physical world coordinates, and vice versa. Calibration is performed using a distortion-free, ideal two-dimensional calibration plane. First, a standard mesh transformation can be used to transform the physical coordinates to the target plane; then, a nonlinear mapping is used to transform these intermediate coordinates to the image plane. The parameters used for the transformation operation can be obtained by imaging a known feature calibration object containing known positional information. The nonlinear transformation is achieved by linear interpolation between defined measurement points. Image Preprocessing Figure 5 shows the acquired raw image. Due to noise inherent in the CMOS sensor itself or system disturbances, the raw image contains noise. Therefore, low-pass filtering is performed on the raw image first. A 3×3 template low-pass filter can be used, or other more complex filters, such as adaptive filters, can be selected. Figure 5. Edge Detection of Original Acquired Image High-precision edge detection of the image is achieved using Newton's interpolation method. The specific calculation steps are as follows: • Search for the image edge transition zone: Calculate the vector. Based on the position of the image edge, search along the rows or columns corresponding to the gray values ​​from the bright area to the dark area. If the decrease in gray value between two adjacent points is greater than a threshold (the threshold should be determined experimentally), then that point is considered the starting node of the image edge transition zone. The transition zone contains 3-4 nodes, which are defined as a one-dimensional array. The starting node of the image edge transition zone is used as the first item, and the gray values ​​of the image edge from bright to dark are stored sequentially along the rows or columns of the gray value matrix. • Implement the image edge light intensity function using the Newton interpolation function. Software demodulation: Let vector u[m] = {u1, u2, ..., un}, m = 0, 1, ..., n. The forward 5-order interpolation at the base point m=0 is: D1u0=u1-u0 D2u0=u2-u1+u0 D3u0=u3-3u2+u1-u0 (1) D4u0=u4-4u3+6u2-4u1+u0 D5u0=u5-5u4+10u3-10u2+5u1-u0 Let t be a continuous variable in [0.5], then the fifth-order Newton forward interpolation function is: v(t)=u0+tD1u0+(t-1)D2u0/2+t(t-1)(t-2)D3u0/6+t(t-1)(t-2)(t-3)D4u0/24+t(t-1)(t-2)(t-3)(t-4)D5u0/120 (2) The coordinate formula (2) for determining the image edge feature points gives the continuous function representing the image edge position. Taking its second derivative, we get: d2u/dt2=D2u0+(t-1)D3u0+(12t2-36t+22)D4u0/24+(20t3-120t2+210t-100)D5u0/120 (3) Its zero intersection point (d2u/dt2=0) is the feature point. Figure 6 shows the effect of edge detection. Figure 6 Edge detection effect Diameter calculation The outer diameter and inner diameter of the circle are calculated by the circle detection algorithm. Due to space limitations, the specific algorithm will not be described in detail here. In the experiment, a lens with f=35mm was used, and LED ring light source was used for coaxial illumination from the bottom. The image resolution was 640×480, and the image size was 3.6mm×2.7mm. The system was calibrated to 0.0375mm per pixel in the XY direction. Ten tests were performed on a component with a nominal outer diameter of 15mm and an inner diameter of 9mm. The average outer diameter was 401.6 pixels (15.06mm), and the average inner diameter was 241.3 pixels (9.049mm). Experimental Results Figure 7 shows the physical prototype of our designed vision sensor. It consists of three parts: a motherboard, a power board, and a CMOS circuit board. The data transmission speed was tested using the packet capture program Ethereal. We tested the data transmission amounts of 100kbyte, 200kbyte, and 300kbyte respectively. The experimental results are shown in Table 1. This system can achieve an image transmission speed of 10 frames per second (f/s). Figure 7: Physical prototype of the system. Table 1: Data transmission speed. Experimental results . Conclusion The vision system introduced in this paper, in its hardware system, uses a CMOS image sensor, CPLD timing control, and high-speed DSP and Ethernet high-speed data transmission, forming a typical embedded vision system. A distributed vision inspection network can be formed through the Ethernet interface. For simple vision inspection tasks, the system can meet the requirements of online inspection. Of course, to ultimately complete complex image processing tasks at high speed without a microcomputer, a single DSP is still insufficient. Future improvements will involve adding an FPGA to realize a processing system that integrates FPGA and DSP, as well as a multi-DSP parallel processing system, to achieve a high-speed embedded vision system. References: 1. TMS320C5000 Series DSPs Principles and Applications (2nd Edition), Electronic Industry Press, 2003 2. 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