With the rapid development of information science, data acquisition and storage technologies are widely used in radar, communication, telemetry, and remote sensing. In high-speed data acquisition systems, the data converted by the ADC needs to be stored in memory before further processing. Ensuring fast and accurate data transmission and processing is crucial for achieving high-speed data acquisition. Because high-speed ADCs have very high conversion rates, while large-capacity RAM is relatively slow compared to ADC output speed, maintaining the reliability and real-time performance of high-speed data storage is a challenging problem. This paper proposes a scheme for high-speed data storage and transmission based on multiple RAM chips in an FPGA for data acquisition systems. This scheme is applied to a 1GS/s data acquisition system, realizing the design of a high-speed real-time data storage system using low-cost RAM. Scheme Selection High-speed data acquisition is the standard for ensuring data acquisition accuracy, but data processing often does not require the same speed; otherwise, the hardware requirements would be too high, and the cost would be too great. This necessitates a data buffer unit to effectively store the data and then process it according to system requirements. There are generally three schemes for constructing a high-speed buffer. The first is the FIFO (First-In, First-Out) method. FIFO (First-In, First-Out) memory acts like a data pipeline; data flows in from one end and out from the other, with the first data entering exiting first. FIFOs have two sets of data lines but no address lines, allowing write operations at one end and read operations at the other. Data moves sequentially within the pipeline, achieving high transmission speeds and efficiency. The elimination of address lines also facilitates PCB layout. The disadvantages are that it only allows sequential data reading and writing, making flexible control difficult, and large-capacity, high-speed FIFOs are very expensive. The second type is dual-port RAM. Dual-port RAM has two independent data, address, and control buses, allowing simultaneous reading and writing from both ports without interference. Sampled data can be written to one port and read from the other by the controller. Dual-port RAM also achieves high transmission speeds and has the advantage of random access. The disadvantage is that large-capacity, high-speed dual-port RAM is very expensive. The third type is high-speed SRAM switching. High-speed SRAM has only one set of data, address, and control buses, which can be connected to the A/D converter and controller respectively through tri-state buffer gates. During A/D sampling, the SRAM switches from a tri-state gate to the A/D converter side to write the sampled data. After A/D sampling is complete, the SRAM switches back to the controller side for reading and writing. The advantage of this method is that the SRAM can be randomly accessed, and there are readily available high-speed SRAMs with larger capacities. To reduce costs, a third method is used to achieve large-capacity data storage. Considering the requirements of a 1GS/s data acquisition system, the storage depth is 4MB. An ISSI static RAM is selected, consisting of eight IS61LV25616 chips to store 4MB of test data. The system structure is shown in Figure 1. Figure 1: Data Storage Principle Block Diagram. Data Storage Design ● Data Flow Control: The ADC has a dual-channel conversion rate of 500MS/s and an 8-bit vertical resolution. The converted data output is a differential output in both I and Q directions for each channel. Driven by a 500MHz differential clock, a real-time sampling rate of 1GS/s can be achieved. The four converted data streams output by the ADC are each 250MS/s. The IS61LV256 series RAM operates at speeds of 10ns or 12ns, requiring data to be buffered by the FPGA before being stored in RAM. The IS61LV25616 series RAM chip has 16 data lines, an 18-bit address width, and control signals for read (RD), write (WR), and chip select (CS). Eight RAM chips are connected in parallel to the FPGA to form the data acquisition storage unit. The ADC outputs AI[8...0], AQ[8...0], BI[8...0], and BQ[8...0], each a LVDS output, totaling 32 bits as a group of converted data DATA[31...0], at a rate of 250MS/s. This speed needs to be reduced to a level acceptable to the RAM within the FPGA. A Cyclone II series FPGA is selected, with an internal clock operating at 402.5MHz, supporting single-ended and high-speed differential standard I/O interfaces, which can fully accept a 250MS/s data stream. Using the FPGA's internal D flip-flops as buffers, after four levels of buffering, DBO[127...0] is obtained, thus reducing the data speed to 62.5MS/s. The buffered data is already within the selected RAM's receiving speed range. The resulting 128 bits of data are used as the data lines for eight RAM chips, completing the data flow control. The principle of data buffering is shown in Figure 2. Figure 2 Data Buffer Design ● Address Generator Design Each time data is read or written, the storage location of the data must be provided. The read/write signal is used as the clock counting signal to sequentially generate address signals. NWE is the RAM write data signal, and NOE is the read data signal; both are active low. AB[17...0] is selected as the address signal for the RAM group. CNTEN is the address counter enable signal, determined by the depth of the read/write data. When the read/write operation is not complete, CNTEN=0, allowing the read/write operation to continue; when the read/write operation is complete, the corresponding address signal sets CNTEN to 1, stopping the address counting. The principle of the address generator is shown in Figure 3. Figure 3 Address Generator Design ● Read/Write Data Design After designing the address generation unit for data acquisition, the next step is to coordinate with timing for read/write operations. Figure 4 is the RAM read operation timing diagram. As shown in the figure, after specifying the address to be operated on, setting the chip enable signal OE and the chip select enable signal CE to be active allows data to be read from the corresponding address on the data lines. Figure 4 RAM Read Data Timing Diagram The operation of a single RAM chip is relatively simple, but to write data sequentially into eight RAM chips, the system must be able to enable the next RAM chip to be operated on after the write operation of the previous RAM chip is completed. The 128 data lines correspond to the data lines of the eight RAM chips. Since the address lines and read/write enable lines are shared, the chip select of each RAM chip needs to be set separately to distinguish which RAM chip is being operated on. The chip select signal can be generated by a decoder. During a read operation, setting the chip select of the corresponding RAM chip to be active allows the stored data to be read. During a write operation, all RAM chip selects can be active, allowing the acquired data to be written to the eight RAM chips simultaneously and in parallel. Based on these descriptions, the chip select signal design is shown in Figure 5. NIOMD is the operation status signal, indicating whether the current operation is read or write. It is set to 1 for reading data, making the chip select signal active. For writing data, it is set to 0, meaning all RAM chips are active and data can be written simultaneously. This design is to meet system requirements; generally, reading data is faster than writing data. Figure 5 shows the simulation verification of the RAM chip select enable signal design. Integrating the above design scheme, along with the design of other control signals, completes the data storage function design of the data acquisition system. Waveform simulation of the above design in Quartus II software shows that by setting the SET value and the corresponding status control signal, the pre-stored data can be read sequentially from the corresponding RAM chips indicated by CS at the VDB terminal. According to the status register settings shown in the figure, the read depth setting register is set to the minimum value SET[4...1]=000, meaning only the first stored data of each RAM chip is read. The maximum value of the address generator is 8. As shown in the figure, when the address generator output value increases to 8, WE jumps to a high level, and the RAM read enable is disabled. Since AB[3]=1, CNTEN=1, the counting clock of the address generator is disabled, the counter stops counting, and one round of data reading operation is completed. The simulation verification results of reading data are shown in Figure 6. Figure 6 Simulation verification of reading data In Figure 6, for the data string DB=0010, 0011, 1010, 1110, 1101, 0011, 1001, 0111 on the current data line, the chip select signal CS is active low. When CS=11011111, the 6th RAM is selected according to the order from low to high bits. At this time, the data read on VDB should be the 6th data value of DB, which is 1010. This is verified from the waveform diagram. Conclusion By utilizing the internal resources of an FPGA and designing flexible logic control, this paper presents a design scheme for high-speed, high-capacity data acquisition, storage, and transmission. This scheme allows for the implementation of real-time, high-capacity data storage requirements using low-cost, simple-to-operate static RAM. The design was successfully applied in a 1GS/s data acquisition module through simulation verification in EDA software.