Abstract: Design and implement an ASIC device that can perform IP protocol functions; discuss the stable working conditions of the device. Any digital industrial equipment can use this IP protocol device to directly connect to the IP-based network. Keywords: Embedded system; IP; ASIC Introduction In order to realize network information processing, embedded systems must have powerful network connection functions. The network connection function of embedded systems not only needs to transmit information, but also needs to have corresponding information recognition capabilities to improve the network security of the system. In recent years, driven by the development of embedded systems and SOC (System-on-a-Chip) technology, microprocessors or single-chip microcomputer systems with embedded IP protocols have emerged [3], laying the foundation for the application of embedded network technology. However, for industrial equipment, especially for instruments and meters used in industrial production, the use of software to embed IP protocols has the disadvantages of not being able to process in parallel and high cost. Therefore, it is of great significance to implement IP protocols in hardware. There are two methods for IP hardware circuit design: embedded processor and ASIC. When designing IP protocols using the embedded processor method, it is necessary to select the corresponding processor and additional circuits, and compile the corresponding software to implement the IP protocol according to the embedded processor. This method can use existing IP protocol software, and software implementation is relatively convenient. Using ASIC technology to design IP protocol is a hardware implementation method of IP, and the execution of IP protocol is all hardware execution. The advantage of this implementation method is that the execution of IP protocol is not affected by software and has a certain anti-interference capability of IP protocol layer. ASIC implementation of IP protocol is a dedicated digital hardware circuit. It only needs to use the corresponding control signal to realize the function of IP protocol and has a relatively high performance-price ratio. In view of the need of industrial equipment for IP protocol, this paper designs and implements an ASIC device that can complete the IP protocol function. For industrial control equipment, this device is a dedicated device to realize IP function. As long as the data to be sent is transmitted to the device, the communication process and control system can be operated in parallel. Any digital industrial equipment can use this IP protocol device to directly connect to the IP-based network. I. Protocol Analysis and IP Circuit Structure Design The function of IP protocol is to pack and unpack data from upper layer protocol and transmit data packets between IP protocol modules until the data packet reaches the destination module [2]. Each host and gateway device in Internet network has IP module. Data packets are transmitted to the destination address through routing processing network address between modules. The data packet header format of IPv4 is shown in Figure 1. When providing network layer services, IP uses a unified header so that IPs in each subnet can process data accordingly based on the header. Figure 1 IP Protocol Header Format IP uses the following four key technologies to implement datagram transmission: (1) Type of Service (ToS). ToS is a set of parameters representing the services that the Internet can provide, used to specify the quality of service that the user wants. The type of service is used by the gateway and can be used for a specific network or for the next network to be traversed, or for the next gateway to route the datagram to select the parameters to be actually transmitted. (2) Time to Live (TTL). Time to Live is the time that the user sets for the datagram to be stored during network transmission. The time to live is set by the sender and processed by the route traversed. If the time to live is zero before reaching the destination node, IP will automatically discard the datagram. (3) Options. Options include timestamps, security, and special routing requirements. Options are important for control functions, but generally unnecessary for normal communication. (4) Header Checksum. The purpose of setting the header checksum is to ensure the correct transmission of data. If the checksum fails, IP will discard the entire datagram. It is important to note that, unlike the simple communication protocols used in general industrial control systems, the IP protocol does not immediately notify the sender after detecting a checksum error. Instead, it discards the received segment of the message and leaves the task of correcting the error to the TCP protocol. This approach not only improves communication efficiency but also simplifies transmission quality and ensures program integrity. In designing the IP protocol ASIC hardware circuit, several issues need to be considered: (1) The core processor of the application system uses control signals to operate the IP protocol devices. Therefore, it is necessary to consider how to implement data exchange between the core processor and the IP hardware circuit through hardware circuitry. (2) If the IP hardware is used in terminal devices (such as control devices in industrial control systems) rather than as a switching node, the routing processing part of the IP protocol can be omitted. (3) To ensure the robustness of the IP protocol, the circuit design must pay close attention to the uneven delay of different circuit parts in parallel protocol operation. The delay of all functional circuits should not exceed the allowable range. If necessary, speed should be sacrificed to ensure the correctness of the protocol operation. (4) If the amount of data transmitted each time is small (for example, as an industrial network control system composed of industrial equipment), the packet fragmentation processing in the IP protocol can be ignored. As long as the length of the data sent each time meets the length requirement of an IP datagram, the application system can correctly and error-free use the IP network to transmit data. This not only simplifies the hardware circuit, but also saves the capacity of the buffer memory. Based on the above discussion, the design of the IP dedicated circuit is actually to implement the external handshake and internal pipeline processing circuit through counters, registers, and RAM. Since receiving and sending are independent of each other, the circuit design can divide receiving and sending into two independent parts. Thus, the block diagram of the IP protocol ASIC dedicated circuit is shown in Figure 2. II. Handshake Operation of IP Protocol ASIC Circuit In IP protocol devices, the task of the sending circuit is to add an IP header to the data to be sent, and then send the packaged IP datagram to the MAC layer. The task of the receiving circuit is to perform header verification and decomposition processing on the received IP packets, and finally transmit the data to the microprocessor system. An important issue in designing IP protocol hardware circuits is the datagram receiving and sending mechanism. There are two key points to implementing the IP protocol in hardware: one is pipeline operation, and the other is data storage method. Pipeline operation refers to the implementation of IP protocol operations in a pipeline manner, with each operation step being processed in parallel. As a network layer protocol, the speed of IP protocol operation depends on two factors: one is the datagram storage method, and the other is the MAC layer's transmission and reception speed. From the perspective of the IP layer, since the access network of the IP network operates in full-duplex mode, the working clock of the hardware device must be based on the transmission and reception clock. In this design, the application system calls the IP protocol signal as the operation enable signal for the transmission circuit, and the MAC layer calls the IP protocol signal as the transmission and reception trigger synchronization signal. The parallel control technology of synchronous trigger clock is adopted to realize the pipelined parallel processing of IP protocol operation steps. There are two ways to store data in the datagram: (1) IP protocol dedicated RAM method. When using this method, the IP protocol needs to have dedicated receiving and transmitting RAM. During the transmission operation, the application system first writes the data to be sent into the IP dedicated RAM, and then calls the IP protocol to perform the transmission processing. During the reception operation, the MAC layer writes the received IP protocol datagram into the IP dedicated RAM, and then the IP protocol processes it. (2) System RAM method. This approach does not require dedicated RAM for the IP protocol; the IP protocol hardware uses RAM from the application system or MAC layer via handshake lines. Comparing the two approaches: the first approach allows RAM to be designed internally within the IP protocol circuitry, without occupying application system and MAC layer resources, but it requires an interface circuit for data transmission between the system and the IP protocol circuitry; the second approach does not require dedicated RAM, thus simplifying the IP protocol circuitry, but it necessitates designing suitable interface circuitry between the IP protocol circuitry and the application system and MAC layer to meet the requirements of IP pipelined operation without increasing the resource burden on the application system. The IP protocol hardware designed in this paper adopts a combination of the two approaches: a corresponding number of RAM modules are set within the IP, which serve not only as data RAM for the IP protocol but also as a communication buffer between the application system and the MAC layer. Connected to the microprocessor and MAC layer devices via handshake lines, the clock signal in the handshake lines controls the timing of the transmit or receive pipeline in the IP protocol devices, enabling parallel operation of the entire protocol processing. The circuit module is shown in Figure 3. Figure 3 RAM Control Logic III. Analysis of the Requirements for Uniform Circuit Delay in Pipeline Implementation The characteristic of the hardware implementation of the IP protocol is that protocol operations are parallel, and the basic content of all protocol operations is completed in parallel according to the execution content of the protocol. For example, the data operation during data transmission is as follows: Read 1 byte - Data processing - Send 1 byte Read 1 byte - Data processing - Send 1 byte Read 1 byte - Data processing - Send 1 byte ... To achieve the above operations, in addition to using an external trigger signal as a unified clock, the delay error of each part of the circuit must also be subject to corresponding limitations. As shown in Figure 4, the IP protocol hardware circuit uses a synchronous timing circuit to enable each circuit to work in parallel in a coordinated manner. The operation of the IP protocol is to process the data packets to be transmitted accordingly. Therefore, whether the circuit is normal depends on the stability of the data. If the circuit can enter a stable state within a specified time, there will be no problem in the data processing process; otherwise, the data will undergo uncertain changes, which is called an abnormal operation result of the hardware circuit. IP protocol devices that exhibit abnormal operation results are unstable. The factors affecting the stability of IP protocol devices are the operation time length of each stage of the circuit and the trigger clock period. As shown in Figure 4, the operation time of each circuit level must be less than the trigger signal period, meaning that all operations of the circuit level must be completed within one trigger cycle. According to the finite state machine and sequential logic circuit theory, each processing circuit level must be a synchronous sequential logic circuit. In addition, the operation time of each circuit level depends on the number of cascaded layers and the time delay of each level. Therefore, to ensure the stable operation of IP protocol devices, the following two conditions must be met simultaneously: (1) The processing time of each module circuit level must be less than the minimum trigger period; (2) The internal delay of each module circuit level can meet the processing time requirements. As a hardware circuit, its processing speed is actually the data transmission speed in the logic circuit. Therefore, the working time of each logic module circuit level can be determined by calculating the maximum time delay of data transmission through the logic gate. In the pipeline operation of IP protocol, the external trigger clock period is TCLK, the transmission delay time of each module circuit is ti, the edge action time of the ASIC circuit using MOS device is tp, the internal transmission of each module goes through N levels of circuits, and the delay of each level is Δti. Then the total delay of each module circuit is ti=NΔti. To ensure the stable operation of the device, TCLK>ti=NΔti is required. Conclusion Microprocessor or single-chip microcomputer system with embedded IP protocol is the basic technology for embedded network technology application[2]. However, the use of software to embed IP protocol in industrial equipment has the disadvantages of not being able to process in parallel or being too expensive. This paper proposes a dedicated IP protocol device to overcome these shortcomings for industrial equipment that needs IP protocol, and provides industrial equipment with a practical network technology with a high performance-price ratio. Any digital industrial equipment can use this IP protocol device to directly connect to the IP-based network. For hardware-implemented IP protocol, the parallel operation of its digital circuit system must ensure the stability of data processing. According to the finite state machine and sequential logic circuit theory, each level of processing circuit that implements parallel operation must be a synchronous sequential logic circuit. Designing IP protocols using ASIC technology is a hardware-based approach, employing parallel operation to implement IP protocols. This ensures that the IP protocol execution is unaffected by software and system interrupts, and also provides a certain level of anti-interference capability at the IP protocol layer. Since ASIC-implemented IP protocols are dedicated digital hardware circuits, their functionality can be achieved simply through corresponding control signals, resulting in a relatively high performance-price ratio. References : 1. Douglas EC, David L S. Internetworking With TCP/IP Vol. Ⅰ: Principles, Protocols and Architecture. Second Edition. Department of Computer Science, Purdue University, 1998(8). 2. Gary RW, W Richard S. TCP/IP Illustrated, Volume 2: The Implementation. Addison Wesley Publishing Company, 1995. 3. Embedded Systems Papers. China Embedded Systems Symposium, 2000.