Abstract: Embedded intelligent motion control technology encompasses multiple disciplines, covering embedded technology, computer technology, intelligent control technology, detection technology, and motion control technology. Based on the current situation in China, this paper designs an embedded intelligent motion control system based on ARM and FPGA. The paper discusses the main components of the industrial motion controller, analyzes the key technologies frequently used in industrial motion controllers, and presents a complete hardware and software structure design. Keywords: Motion control; Embedded; ARM; FPGA 1 Introduction Currently, motion control technology has evolved from traditional CNC machining technology into advanced motion control technology with an open structure that can be quickly reconfigured for specific applications. Motion control systems have also evolved from using microcontrollers or microprocessors as core components to open motion control systems using application-specific integrated circuits (ASICs) and DSPs or FPGAs as core components. Combined with PC application software, bus technology, and embedded system technology, motion control, as an important branch of automation technology, has been increasingly widely and significantly applied. Based on in-depth study of the key CNC technologies in industrial motion control, several commonly used motion control schemes were compared, and a new embedded motion control system based on ARM chip was proposed. The design scheme of motion control based on ARM and FPGA was determined, and the overall design structure of the controller was planned. 2 Control Circuit Hardware Design Planning In this motion control system design, the core control chip is the dedicated industrial application ARM chip LPC2132 produced by Philips. The external expansion I2C storage chip AT24C512 stores the FPGA configuration code and two RS485 communication channels, forming the core control unit. The FPGA is connected in parallel with the ARM chip as the main device of the hardware fine interpolator, so as to complete the main parallel configuration of the high-speed fine interpolator when the system is powered on. The design goal of this system is shown in Figure 1: Figure 1 System Design Goal Block Diagram Based on the embedded motion control system, the overall structure is divided into the following parts: (1) Power supply circuit design. (2) ARM main control circuit peripheral expansion design. (3) FPGA high-speed hardware fine interpolator design. (4) Connection between the control board and the I/O interface board. 3. Control Circuit Hardware Design 3.1 Introduction to the LPC2132 Chip The LPC2132 is a microcontroller based on a 32/16-bit ARM7TDMI-STM CPU with real-time emulation and embedded tracing, and features 64KB of embedded high-speed Flash memory. Its 128-bit bandwidth memory interface and unique acceleration architecture allow 32-bit code to run at maximum clock rates. Applications with strict code size control can use 16-bit Thumb mode to reduce code size by over 30% with minimal performance loss. Its small package and extremely low power consumption make the LPC2132 ideal for small systems. Multiple 32-bit timers, two 10-bit 8-channel ADCs, one 10-bit ADC, a PWM channel, 47 general-purpose I/O ports, and up to nine edge- or level-triggered external interrupts make it particularly suitable for industrial control and medical systems. 3.2 Power Supply Circuit Design Since the voltage commonly used in industrial environments is +24V, while chips such as ARM and FPGA require lower voltages such as 3.3V and 2.5V, this design mainly focuses on voltage conversion and supplying power to the core voltage and port voltages of the ARM and FPGA chips respectively. Figure 2 shows the power supply circuit design schematic. As can be seen from the schematic, a MORSUN isolated power supply is used to first convert the 24V DC to +5V, and then supply it to two AS1117-3.3 chips and one AS1117-2.5 chip respectively. One AS1117-3.3 generates 3.3V to supply the ARM chip, while the other supplies the I/O port operating voltage of the FPGA. The AS1117-2.5 chip generates 2.5V to supply the FPGA core. Because a stable power supply voltage needs to be provided to the core module during power-on, electrolytic capacitors or bipolar capacitors are added to both the input and output terminals for voltage regulation and filtering. The LEDs in the figure are mainly used to detect the power-on process. 3.3 External Storage Circuit Design In motion control systems, FPGAs play a crucial role. They are key to achieving precise interpolation in the entire laser engraving CNC system and are also the core component for generating positioning pulses in rotary screen printing motion control systems. As a Spartan-II series FPGA, it uses SRAM technology internally, storing its configuration data in SRAM. Due to the volatility of SRAM, the data (ICR) must be reconfigured each time the system is powered on; the system can only function normally if the data is correctly configured. After power failure, the device completely returns to a "blank" state. Therefore, in this situation, the system needs an external storage chip to store the configuration file. Serial E2PROM is an online electrically erasable and writeable memory, characterized by its small size, simple interface, reliable data storage, online rewriting capability, and low power consumption. The commonly used bus form for serial EPROM is the I2C bus. The E2PROM chip used here is the AT24C512 chip manufactured by Atmel. This chip provides 64K of memory and features non-volatility, small size, programmability, erasability, and low-voltage operation. Up to four AT24C5121331 chips can be connected to a two-wire serial bus. The LPC2132 chip used has dedicated pins for expanding standard I2C devices. The hardware circuit diagram for its connection with the ARM is shown in Figure 3. Figure 3 shows the connection diagram between LPC2132 and AT24C512. As can be seen in the figure, 2K pull-up resistors are added to the data and clock lines of the I2C bus. This is determined by the requirements of the ARM's I/O port structure. In the LPC2132, since the I/O port with I2C bus function is an open-drain output, pull-up resistors of 1K to 10K are required when using the I2C bus function. In this design process, two E2PROM memory chips were added. One chip was used as the hardware interpolator for the motion control system, while the other chip was used to generate the precise positioning pulses for the motion control system. 3.4 Input/Output Port Design In this design, there are 8 input switch quantities, 8 output switch quantities, 4 encoder inputs, 4 frequency converter pulse outputs, and multiple input/output ports expanded from the FPGA. In order to effectively prevent interference from entering the control core of the motion control system, optocoupler isolation was used. Optocoupler isolation has the following advantages: (1) The input impedance is small, generally between 100Ω and 1KΩ. The internal resistance of the interference source is generally very large, so the noise from the voltage divider to the optocoupler is very small. (2) The internal light-emitting diode of the optocoupler works by current, while the interference current cannot drive it under normal circumstances. Therefore, the interference noise can be effectively suppressed. (3) The distributed capacitance in the input and output circuits is extremely small, generally 0.5-2pF, and the insulation resistance is very large. It is difficult for interference on one side of the input circuit to be fed to the output end through the optocoupler. The input/output ports connected by optocouplers are shown in Figure 4-4: (a) Low-speed switching quantity (b) High-speed switching quantity Figure 4 Input/output ports connected by optocouplers In low-speed switching quantity, as shown in Figure 4(a), a surface-mount low-speed optocoupler MOCD217-M is used. It is a product of Motorola and is a dual-channel optocoupler with low input current. The reason for adding resistor R3 before connecting the six input ports is that some I/O ports in the ARM are open-drain, which prevents excessive current during input/output processes from burning out the corresponding ports. As shown in Figure 4(b), in high-speed switching quantity, the HCPL0661 dual-channel optocoupler is used for expansion. It is a product of Agilent Technologies, and its switching rate can reach about 10M, which can be applied to various high-speed pulse input/output applications. 4.2.5 FPGA Configuration Methods In the configuration process of Xilinx Spartan-II series FPGAs, there are three main configuration methods: Boundary-Scan mode, Master/Slave-Serial mode, and Master/Slave-Parallel mode. The following is a simple analysis of the configuration process of these three modes, and a detailed introduction to the Slave-Parallel configuration mode. (1) Boundary-Scan mode. The boundary scan mode adopts the JTAG standard, so it is sometimes called the JTAG configuration mode. This mode has only four dedicated configuration signal lines, namely TCK (clock), TDI (data input), TDO (data output), and TMS (status and control). This mode is similar to the slave serial mode. The configuration process requires the support of an external processor. (2) Master/Slave-Serial mode. Serial configuration means that only one bit of configuration data is accepted for each clock. Serial configuration can be divided into master serial and slave serial modes. If the configuration clock signal comes from the FPGA device to be configured, this mode is the master serial mode. If the configuration clock is provided by an external device, this configuration mode is the slave serial mode. (3) Master/Slave-Parallel mode. In order to achieve fast data loading, Xilinx added a parallel mode to the FPGA device. This mode has an 8-bit configuration data width and requires 8-bit data lines D7-DO. In addition, there are active-low chip select signal (/CS), active-low write signal (WR), and active-high busy signal (BUSY). When the BUSY signal is high, it indicates that the device is busy and cannot perform the next write operation; it needs to wait until the signal goes low. For configuration clocks below 50MHz, this control signal is not required. Parallel mode can be further divided into master parallel mode and slave parallel mode. When multiple devices need to be configured in parallel, slave parallel mode should be selected; when only a single device is configured, master parallel configuration mode is used. In this motion control system, in order to improve the speed of the configuration process, achieve the real-time performance of the high-speed hardware interpolator after power-on, and since only a single FPGA is configured, master parallel configuration is selected here. The connection diagram between ARM and FPGA is shown in Figure 5. Figure 5 Master Parallel Configuration Mode As can be seen from Figure 5, the ARM's P0.2 and P0.3 ports are used to externally expand the AT24C512 E2PROM memory chip. The FPGA connection adopts a parallel connection method, and according to the FPGA parallel configuration rules, the corresponding ports of the ARM are used to connect to the FPGA. The innovative points of this paper: This paper mainly introduces the hardware of the designed motion control system in detail. First, it presents the overall plan of the motion control system. Based on the plan, several important modules are designed in detail. Finally, the development process of the hardware fine interpolator in the system is briefly introduced, and a detailed design description is provided based on this. Then, several important functional modules in the fine interpolator are designed, and detailed implementation methods are given. References: [1] Liu Wensheng, Song Changcai. Application of motion control technology. Vol. 31 No. 6 2005.12: 25-27 [2] Cong Shuang, Li Zexiang. Practical motion control technology. Electronic Industry Press 2006. [3] Huang Yiqun, Zhang Hairong, Yan Caizhong, Chen Xianfeng, Shu Zhibing. New motion control technology. Servo Control 2005.11: 20-24. [4] Zhou Baoyan, Wang Bojun. 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