Design of an Ethernet-based elevator monitoring system

Abstract: Ethernet is an ideal platform for building elevator monitoring systems. This paper introduces an Ethernet-based elevator monitoring system. The system uses the TMS320LF2407A as the main control chip and the RTL8019AS as the Ethernet interface chip, and employs LabVIEW to build the monitoring interface. This provides a solution for applying Ethernet communication technology in elevator monitoring systems.

Keywords: Ethernet; elevator; monitoring; DSP; LabVIEW

I. Introduction

With the development of the national economy, elevators have been widely used. The complexity and dispersed installation of elevator systems have placed higher demands on elevator operation and maintenance. Ethernet, with its large bandwidth, can meet the real-time requirements of data transmission and boasts advantages such as strong versatility and mature technology, making it an ideal platform for building elevator monitoring systems. This paper designs an Ethernet-based elevator monitoring system that combines computer control and network technologies, enabling real-time monitoring of multiple elevators from a control center.

II. Elevator Controller Structure and Ethernet Interface Circuit Design

2.1 Elevator Main Controller Structure

The block diagram of the elevator controller is shown in Figure 1. The elevator controller uses DSP+CPLD as the control core and includes Ethernet interface, RS485 communication interface, CANBUS, and switch input/output circuits.

2.2 Overview of RTL8019AS and TMS320LF2407A Chip Functions

2.2.1 RTL8019AS chip

The RTL8019AS is a highly integrated Ethernet controller manufactured by Realtek that fully supports the IEEE 802.3 standard. It is software-compatible with the NE2000 and also supports Microsoft's PnP specification. The main performance characteristics of the RTL8019AS are as follows:

(1) Compatible with Ethernet II, IEEE 802.3, 10Base5, 10Base2, and 10Base-T;

(2) Full-duplex operation mode, with simultaneous transmission and reception speeds of up to 10Mbps, and a sleep mode to reduce power consumption;

(3) Built-in 16KB SRAM for transmit and receive buffers to reduce the speed requirements of the main processor;

(4) It can connect to coaxial cables and twisted pairs, and can automatically detect the connected medium;

(5) 100-pin TQFP package, reducing PCB size;

(6) LED indicator lights and diagnostic software can be used for simple troubleshooting;

(7) Access protocol CSMA/CD.

2.2.2 TMS320LF2407A Chip

TI's TMS320 series DSP chips are designed to meet the wide range of needs in motor control and other embedded control applications. The TMS320LF2407A utilizes high-performance CMOS technology, reducing the supply voltage to 3.3V and minimizing controller power consumption. It features a maximum frequency of 40MHz, an instruction cycle of 25ns, 32k words of on-chip FLASH program memory, 1.5k words of data/program RAM, 544 words of DRAM, and 2k words of SRAM. The time managers EVA and EVB include a 16-bit general-purpose timer, pulse-width modulation (PWM) channels, CAP and QEP, a watchdog timer, 16-channel 10-bit A/D conversion, a Controller Area Network (CAN) module, a Serial Communication (SCI) interface module, a 16-bit Serial Peripheral (SPI) interface module, a phase-locked loop-based clock generator, and 40 general-purpose input/output pins.

2.2.3 Network Interface Hardware Block Diagram

The Ethernet interface chip RTL8019AS has three operating modes: (1) Jumper mode, where I/O address and interrupt are determined by jumpers. (2) Non-jumper mode, where I/O address and interrupt are determined by the contents of the external EEPROM. (3) Plug and play mode, where I/O address and interrupt are managed by the operating system.

In this design, the first working mode is adopted.

(1) I/O Address: Pull pin 65 JP of RTL8019AS high, i.e., use jumper mode. The base address of RTL8019AS is determined by configuring the four pins BD0, BD1, BD2, and BD3 as 300H. Connect the lower 5 address lines, A15 to A9, A10 to A8, to map RTL8019AS to the DSP's I/O space. The base address 0x8400-0x841F corresponds to the 32 addresses of RTL8019AS.

(2) Interrupts: The interrupts of the RTL8019AS are determined by IRQS0, IRQS1, and IRQS2. This system uses a polling method to determine whether the network chip has received data, so the three pins IRQS0-IRQS2 are left floating.

(3) The DSP and CPLD are powered by 3.3V, while the RTL8019AS is powered by 5V. Therefore, the data bus uses 74HCT16245 to match the levels between the two. However, the output level of the DSP meets the control line level of the RTL8019AS, so they can be directly connected.

(4) Bus mode: The IOCS16B pin of the RTL8019AS is pulled up by a 300-ohm resistor, so that the RTL8019AS works in 16-bit bus mode.

III. Network Interface Chip Initialization and Driver

3.1 Network Interface Chip Initialization Process

The RTL8019AS chip has 32 bytes of control registers, which are read and written to to complete chip initialization. Additionally, the chip contains 16KB of SRAM, located at addresses 0x4000–0x7fff, which can only be read and written via DMA.

(1) Reset: First set RSTDRV to high level, then set it to low level. The interval between the two operations should be at least 100ms to ensure a successful reset. Then perform a hot reset, which involves reading and writing the network card reset port in sequence.

(2) Select page register 0 and set CR = 0x21. Set data structure register DCR = 0x49, transmit status register TCR = 0x00, receive status register RCR = 0x1F, receive start page register PSTART = 0x46, receive end page register PSTOP = 0x80; boundary page register BNRY = 0x46.

(3) Select page register 1 and set CR = 0x61. Set the physical address register and multicast address register of RTL8019AS, and set the current page register CURR = PSTART + 1;

(4) Select page register 0 and set CR = 0x21. Set interrupt status register ISR = 0xFF; interrupt mask register IMR = 0xFF; send configuration register TCR = 0x00;

(5) Set CR=0x22, and the chip will enter the working state.

3.2 Ethernet packet reception and transmission process

The RTL8019AS has 16KB of RAM with an address range of 0x4000 to 0x7FFF, consisting of 64 pages. These 64 pages of RAM are used to receive and send data packets. The receive buffer and transmit buffer are set through the page start register PSTART and the page stop register PSTOP.

3.2.1 Ethernet packet reception process

Two registers control the operation of the receive buffer: the current pointer register CURR and the boundary pointer register BNRY. CURR is the pointer to the write buffer of the RTL8019AS, pointing to the page to be written. BNRY is the read pointer, pointing to the page that the user has already read. Therefore, the distance between the CURR and BNRY pointers can be used to determine whether a new data packet has been received. When CURR and BNRY+1 are not equal, it indicates that a new data packet has been received. In the received data packet, there are 4 bytes of additional information before the correct data packet and 4 bytes of CRC checksum at the end. The first 4 bytes of the data packet: The first byte indicates the status of the received packet. The second byte indicates the page address where the next data packet will be stored, and the BNRY register is updated based on this value. The next two bytes indicate the size of the data. When processing a data packet, these 4 bytes must be read first. The first byte is used to determine whether the data packet has been received correctly. If the data packet has been received correctly, the DMA counter value is modified according to the value of the last two bytes. Then, the entire data packet is read, and the BNRY register is updated to prepare for the reception of the next data packet.

The flowchart of the network card receiving process is shown below:

3.2.2 Ethernet Packet Transmission Process

Sending data packets is relatively simple. Just transfer the prepared data to the sending buffer using DMA, then set the sending length and the start page of the transmission, and start the sending process.

The network card sending flowchart is shown below:

IV. Monitoring Interface Design

The elevator monitoring interface was developed using LabVIEW 7 Express. LabVIEW is the most representative graphical programming development platform in the field of virtual instrumentation, mainly used in instrument control, data acquisition, analysis, and display, and is compatible with various operating system platforms. LabVIEW uses a powerful graphical language (G language) for programming, geared towards test engineers rather than professional programmers. Programming is very convenient, the human-computer interface is intuitive and user-friendly, and it features powerful data visualization and analysis capabilities as well as instrument control capabilities. In the LabVIEW development environment, users can create 32-bit compiled programs, thus providing faster execution speeds for routine data acquisition, testing, and measurement tasks.

V. Conclusion

This paper presents an elevator monitoring system based on Ethernet technology, designed using the TMS320LF2407A and RTL8019AS, which enables elevators to connect to the Ethernet network. Monitoring elevator operation via Ethernet has significantly improved work efficiency and the working environment, yielding positive results after trial operation.

The author's innovation lies in applying Ethernet technology to an elevator remote control system, which achieved the expected results through laboratory testing.

References:

[1]Realtek Full-Duplex Ethernet Controller with Plug and Play Function (RealPNP) REALTEK SEMI-CONDUCCTOR CO.,LTD 2000.08

[2] Liu Heping. TMS320LF240x DSP C Language Development and Application [M]. Beijing University of Aeronautics and Astronautics Press, 2002.

[3] Yang Leping. Advanced LabVIEW Programming. Tsinghua University Press [M], 2003

[4] Luo Zhijia. Application of Ethernet-based distributed data acquisition and monitoring system [J]. Microcomputer Information. 2006.