Implementation of CAN bus communication in digital relay protection systems

Abstract: This paper introduces the media access method and technical characteristics of CAN bus, analyzes the feasibility of CAN bus application in digital relay protection system and the nature of the transmitted data stream, and presents the hardware configuration scheme and software design flow of DSP McBSP (Multi-channel Buffered Serial Interface) interface with CAN controller .

Keywords: CAN bus; digital relay protection; multi-channel buffered serial interface

CAN bus is a serial data communication protocol developed by the German company BOSCH in the early 1980s to solve the data exchange between many control and test instruments in modern automobiles. Due to the high reliability and unique design of CAN bus, it is now widely used in power systems, mobile devices, medical and test instruments, and is recognized as one of the most promising fieldbuses. In November 1993, the International Organization for Standardization (ISO) officially promulgated the international standard ISO11898 for high-speed communication controller local area network (CAN)[2], paving the way for the standardization and promotion of CAN bus.

1. Feasibility Analysis of CAN Bus Application in Digital Protection Systems

CAN bus is a multi-master bus, meaning that each node can become a master and can communicate with each other. All nodes on the bus share the communication medium, so it is necessary to solve the conflict problem caused by the nodes competing to use the bus. CAN bus adopts a unique nondestructive carrier sense multiple access (CSMA/CD) bus arbitration technology based on message static priority [3].

The message header identifier defines a static message priority. Any node can begin transmitting messages as long as the bus is idle. If two or more nodes begin transmitting messages simultaneously, a bus access conflict occurs. This conflict can be resolved through bitwise arbitration of the identifier. During arbitration, each transmitter compares the level of its transmit bit with the level of the bus being monitored. If the levels are the same, the node can continue transmitting; otherwise, it stops transmitting.

On the CAN bus, voltage levels are represented by "dominant" (logic "0") and "recessive" (logic "1"). When both "dominant" and "recessive" are present simultaneously, the bus voltage level becomes "dominant." If node 1 sends a "recessive" voltage level while node 2 sends a "dominant" voltage level, the bus voltage level detected by both nodes will be "dominant." In this case, node 1 loses arbitration and must exit the transmitting state, while node 2 wins the arbitration and can continue transmitting messages unaffected. This non-destructive bus arbitration mechanism of the CAN bus ensures that neither message transmission nor time loss occurs.

In addition to the features of the non-destructive bus arbitration mechanism mentioned above, the CAN bus also has the following significant features[4]:

① The CAN bus has a comprehensive error handling mechanism, including listening, CRC check, bit stuffing technology, frame format checking, and some corresponding criteria. On the CAN bus, any node that detects an error will send a bit stream called an "error flag," marking the corrupted message. This message will be invalidated and will automatically begin retransmission. Therefore, its reliability is very high.

② The data segment length is a maximum of 8 bytes, which will not occupy too much bus time, thus ensuring real-time communication. For example, the serial rate of the MCP2510 CAN controller is 1M, and the longest message transmission delay is 64µs (8×8/1=64). However, this also reflects its limitation in transmitting long messages.

Considering that the switching signals in the digital relay protection system, including circuit breaker position status signals, protection activation signals, opening and closing signals, and alarm signals, are all small data amounts of a few bytes, but have high requirements for real-time performance and reliability, the application of CAN bus to transmit switching signals in the protection system can give full play to the technical advantages of CAN bus.

2. Design of the DSP's McBSP and CAN controller interface

The CAN bus communication module consists of the MICROCHIP CAN bus controller MCP2510[5] and the TI CAN bus transceiver SN65HVD232[6], as shown in Figure 1. The MCP2510 is a CAN controller with an SPI interface, compatible with the CAN2.0A/B protocol, and supports the passive/active versions of CAN1.2, CAN2.0A, and CAN2.0B protocols. It implements the logical link control and media access control of the CAN bus, and can send and receive standard and extended messages with a bit rate of up to 1Mbps. It also has acceptance filtering and message management functions, including 3 transmit buffers and 2 receive buffers, which reduces the management burden of the microcontroller (MCU). The SN65HVD232 is the driver interface between the CAN protocol controller and the physical bus, providing different transmission capabilities for the bus and different reception capabilities for the CAN controller. It is compatible with the ISO11898 standard.

This paper selects the high-performance C54 series DSP from TI as the control core, specifically the TMS320VC5410A, with a working frequency of 160MHz. The TMS320VC5410A provides a high-speed, bidirectional, multi-channel buffered serial interface McBSP and an SPI (Industry Standard Serial Peripheral Interface) interface for the MCP2510. The connection relationship between the two is shown in Figure 2.

McBSP is powerful and complex. To achieve communication between the two, it is crucial to properly configure the various registers of McBSP, including master-slave mode selection, generation of clock signals and frame synchronization signals, edge selection for data transmission and reception, and timing coordination. These will be discussed in detail below.

The connection between the clock and frame synchronization signals indicates that the McBSP operates in Master mode, and the MCP2510 operates in Slave mode. The McBSP's transmit clock is generated by the DSP's internal sampling rate generator (transmit clock mode bit CLKXM=1), the sampling rate generator clock is generated by the DSP's internal clock (sampling rate generator clock mode bit CLKSM=1), the McBSP's receive clock is driven by the transmit clock (receive clock mode bit CLKRM=0), and the MCP2510's clock is provided by the McBSP. In short, all clock sources are the DSP's internal clock. Simultaneously, the transmit frame synchronization signal FSX is generated by the data copying operation from the McBSP's internal register DXR to XSR (transmit frame synchronization mode bit FSXM=1, sampling rate generator transmit frame synchronization mode bit FSGM=0), and the receive frame synchronization signal is driven by the transmit frame synchronization signal (receive frame synchronization mode bit FSRM=0).

Based on the clock and synchronization signal flow analysis in the internal connection diagram shown in Figure 3, the McBSP's internal clock signals (Internal CLKX, Internal CLKR) and frame synchronization signals (Internal FSX, Internal FSR) are generated and stopped synchronously with the MCP2510's clock signal and chip select signal. The McBSP's internal transmit frame synchronization signal, Internal FSX, transitions from low to high, while the connected MCP2510 chip select signal transitions from high to low, with opposite phases. Therefore, the polarity bit FSXP of the transmit frame synchronization signal in the McBSP's internal register is 1. Since the McBSP's internal frame synchronization signal, Internal FSR, must be consistent with Internal FSX, Internal FSR must also be inverted compared to the MCP2510 chip select signal. The polarity bit FSRP of the receive frame synchronization signal is 1.

The McBSP transmits data on the rising edge of its internal transmit clock (Internal CLKX) and receives data on the falling edge of its internal receive clock (Internal CLKR). Conversely, the MCP2510 receives data on the rising edge of its external clock (CLK) and transmits data on the falling edge of its external clock (CLK). Based on the previous analysis of clock and frame synchronization signals, we know that Internal CLKX, Internal CLKR, and CLK share the same clock. To ensure reliable data transmission and reception, the transmit clock polarity bit CLKXP = 1 (Internal CLKX is inverted compared to CLKX) and the receive clock polarity bit CLKRP = 1 (Internal CLKR is inverted compared to CLKR). This way, one side transmits on the rising edge and the other receives on the falling edge, ensuring reliable communication; otherwise, if both sides transmit and receive data on the same edge of the same clock, reliable communication cannot be guaranteed.

3 Communication Software Flow Design

The DSP transmits data through the SPI interface between the McBSP and the MCP2510. The MCP2510's transmit register acts as a mapping register to the transmit buffer; the DSP accesses the transmit register to transfer data to the transmit buffer. The MCP2510 has six filters; data filtered by the receive filters on the CAN bus is first placed into the receive buffer. The receive register acts as a mapping register to the receive buffer; the DSP accesses the receive register to receive data from the buffer.

The communication process between the DSP and MCP2510 consists of two steps: ① Based on the conclusions drawn from the above analysis, the control registers of the McBSP are configured. The transmission process is as follows: data is written into the McBSP's transmit register DXR, and then the data is shifted out via pin BDX through the transmit shift register XSR. The reception process is as follows: data received through the McBSP pin BDR is shifted into the receive shift register RSR, and this data is copied to the receive buffer register RBR, then copied to the receive register DRR, and finally read by the DSP. ② The communication between the McBSP and MCP2510 exchanges data according to the clock and frame synchronization signals configured internally within the McBSP.

To improve communication efficiency, the DSP adopts an active transmission mode, connecting the DSP's HD port (configured as an I/O port) to the MCP2510's TXRTS terminal to select the transmission buffer unit. The transmission process is shown in Figure 4. The reception mode adopts an interrupt mode. Once the MCP2510's receive buffer is full, an interrupt signal is sent to the DSP to notify the DSP to read the data. The reception process is shown in Figure 5.

4. Conclusion

This paper analyzes the feasibility of using the CAN bus in digital protection systems, highlighting its advantages of high real-time performance and reliability in short-byte communication. It presents the hardware configuration scheme and software design flow for the DSP's McBSP interface with the CAN controller. Data from actual communication experiments in a digital protection system demonstrates that the CAN communication scheme is efficient and reliable, meeting the real-time communication requirements of digital relay protection and fully leveraging the advantages of the CAN bus.

The author's innovation lies in discussing the feasibility of CAN bus application in digital relay protection based on the characteristics of CAN bus. The author also analyzes in detail the internal clock and synchronization signal flow of the high-speed, bidirectional, multi-channel buffered serial interface McBSP of TMS320VC54X DSP. From this, the author derives the master-slave mode selection of McBSP interface with CAN controller, the generation of clock signal and frame synchronization signal, the edge selection of data transmission and reception, and the configuration of key register bits such as timing coordination.

References:

[1] Li, Mao Qin, Tinggao Yan, Shixiao. Application of MCP2515 in Smart CAN Node[J], Control & Automation, 2005, 21(7):37-39

[2]CAN, International standard 11898: Road Vehicles – Interchange of Digital Information –Controller Area Network for High-Speed ​​Communication, ISO 11898, Nov.1993

[3] BOSCH.CAN Specification Version 2.0.1991

[4] Wu Kuanming. CAN Bus Principles and Application System Design [M]. Beijing: Beijing University of Aeronautics and Astronautics Press, 1996.

Wu Kuanming. The CAN BUS Principium and design for application system [M] .Beijing: PUAA Press, 1996

[5]Microchip Technology, Inc.MCP2510 Stand-Alone CAN with SPI Interface.2002

[6] Texas Instruments.3.3V CAN Transceivers.2002