1. Introduction Raster digital display systems are mainly used in ordinary machine tools, directly displaying the length value processed by the machine tool, which helps improve processing accuracy and efficiency. Currently, most grating digital display systems on the domestic market use foreign integrated circuits, resulting in high R&D costs and inconvenience for operators. To address this situation, a new type of grating digital display system based on MCU+CPLD has been developed. This system features high counting accuracy, low cost, convenient operation, and rapid upgrades. It can process orthogonal pulses up to 5 MHz/s and effectively store the current length value when power is off. Its digital tube can display key length values, and the dot-matrix LCD screen can display relevant prompts. 2. System Working Principle The orthogonal pulse processing logic circuit is implemented using a CPLD, while a reversible counter is used to process the orthogonal pulses output by the grating ruler. The high-speed parallel processing capability of the CPLD ensures that the grating ruler output signal is sampled without omission, thus ensuring the reliability of the counting. The value of the reversible counter is converted into the length value processed by the machine tool after a series of calculations by the MCU. The MCU then sends the length value back to the CPLD for display on the digital tube. In addition, the CPLD also has 7×8 keyboard key detection and debouncing functions, sending the processed reliable key presses to the MCU. The MCU is mainly used for LCD screen display control, power-off data saving, and complex mathematical calculations. The system working principle block diagram is shown in Figure 1. 3. Quadrature Pulse Signal Acquisition and Processing 3.1 Quadrature Pulse Acquisition The grating ruler outputs a set of quadrature pulse signals, namely two square waves with a phase difference of 90°, as shown in Figure 2. When the grating ruler moves forward by one grating pitch, the grating ruler outputs a 00-01-11-10-00 cycle, and the phase of the A-channel square wave leads the B-channel by 90°; when the grating ruler moves backward by one grating pitch, the grating sensor outputs a 00-10-11-01-00 cycle, and the phase of the A-channel square wave lags the B-channel by 90°. Analysis of the logic states of the A and B channels reveals that only one signal of the A and B channels undergoes a logic state change at any given time. If the states of paths A and B are the same before the logic state change, then the logic states after the change will definitely be different; if the logic states of paths A and B are different before the change, then the logic states after the change will definitely be the same. By simply XORing these two signals, the direction signal updown of the grating ruler's movement and the counting pulse cp proportional to the movement distance can be extracted. As shown in Figure 2, moving the grating ruler by one grating pitch will output four cp pulses, increasing the minimum resolution of the system measurement to 1/4 of the grating pitch, commonly referred to as four-phase splitting or four-fold frequency multiplication. The CPLD detects the states of paths A and B on the rising edge of each clock cycle. First, it XORs the currently detected states A0 and B0 with the previously detected states A1 and B1, then XORs the two XOR values ​​again. If the final XOR value is 1, it indicates that paths A and B have changed, and a high-level counting pulse cp with a width of one clock cycle is input to the reversible counter, as shown in Figure 3. 3.2 The reversible counter inputs the extracted direction signal updown and the counting pulse cp to the reversible counter to count the quadrature pulses output by the grating ruler. The VHDL program for the reversible counter module is as follows: 3.3 Value of clk Since the sampling clock clk of the CPLD must be greater than 8 times the quadrature pulses output by the grating ruler, the system will not lose signals. The system design uses a 40 MHz active crystal oscillator as the sampling clock source for the CPLD, and the maximum frequency of the grating sensor output signal that can be recorded is 5 MHz. If a 50 lines/mm grating ruler is used, after the CPLD performs four-phase subdivision, the maximum non-missing processing speed of the grating ruler connected to the system is calculated to be 20 μm × 5 MHz = 100 m/s, and the minimum resolution is 5 μm. This far exceeds the machine tool's operating speed limit and fully meets the actual requirements. 3.4 Introduction to EPM240 The Altera EPM240 is selected as the CPLD. The EPM240 is a member of the MAX II series of devices. The architecture of the MAX II CPLD series makes it the lowest in power consumption and cost per I/O pin among all CPLD series devices; supporting internal clock frequencies up to 300 MHz, and targeting general-purpose low-density logic applications, the MAX II CPLD can replace high-power and high-cost ASSPs and standard logic CPLDs. The EPM240 contains 240 logic elements (LEs), equivalent to 192 macrocells; 8192 bits of user Flash memory, meeting the requirements for small-capacity information storage; a maximum number of user I/Os is 80, with a maximum speed of 4.5 ns, fully meeting system design requirements. 4. MCU Power-Down Data Storage Power-down data storage is another important function of the system design, requiring high reliability. The system should save the current position information of the grating ruler when power is lost, and restore the system by recalling the position information saved during the next power-on. Therefore, at the moment of power failure, the power-down alarm circuit will respond quickly, sending an alarm signal to the MCU; after detecting the alarm signal, the MCU will immediately process it and store the current position information of the grating ruler into the EEPROM. Its hardware circuit is shown in Figure 4. To improve the MCU's power-down response speed and enhance system reliability, the system design adopts the new enhanced 51 microcontroller STC-89C516RD. This device has 1 KB RAM and up to 64 KB of ROM, ISP function, and two selectable instruction cycle modes: 6 clock and 12 clock. Using a 20 MHz crystal oscillator, when programming in 6 clock mode, the program execution time per instruction cycle is only 0.3 μs, which is much faster than the operating speed of ordinary 51 microcontrollers with a maximum crystal oscillator of 24 MHz. Therefore, the execution time of the data storage program is greatly shortened. 4.1 The power-down alarm circuit uses the ultra-small high-precision voltage detector S80848, with an internal detection voltage fixed at 4.8 V, an accuracy of ±2%, and a maximum response time of 60 μs. The S80848 uses a standard 5 V power supply, outputting a high level when the power supply is normal; when the power supply voltage drops to 4.8 V, it outputs a low level. Connect the output pin of the S80848 to the INT0 of the MCU, and set the MCU's INT0 to level trigger. Therefore, the MCU will enter an INT0 interrupt whenever the power supply voltage drops below 4.8V, and the MCU will save its position information in the interrupt routine. 4.2 EEPROM Selection: After the MCU completes its write operation to the EEPROM, the EEPROM needs a maximum self-write time of 10ms to write the information to the memory cell. To utilize more time for EEPROM self-write, a low-voltage EEPROM, namely the AT24C64-2.7V, is selected. Its operating voltage is 5.5V to 2.7V, its capacity is 64KB, each page is 32B, and its maximum write count is 1,000,000. 4.3 Power-Down Time Calculation: The STC89C516RD, with an operating voltage of 4.5V to 5.5V, is selected. When the power supply voltage drops below 4.5V, the MCU cannot operate reliably. The MCU's INT0 interrupt service routine can only utilize the time during which the power supply voltage drops from 4.8V to 4.5V; all processing must be completed within this time. Therefore, interrupt program design should aim to minimize execution time. The interrupt should first store all stored data into an array, then write all elements of that array into the AT24C64. The number of elements in this array must be less than the length of one page of the AT24C64, i.e., less than 32 bytes. When the output voltage is 5 V, the maximum current is Imax = 0.8 A, the equivalent load R = 5/I = 6.25 Ω, and the capacitor C connected in parallel with the 5 V power supply is 4700 μF. Therefore, the system time constant is τ = RC = 0.029 s. Assuming a power outage occurs at t = 0, according to the formula u(t) = Vccexp(-t/τ) = 5exp(-t/0.029), we know that at t = 1183 μs, the power supply voltage Vcc drops from 5 V to 4.8 V; at t = 3055 μs, Vcc drops to 4.5 V; and at t = 17869 μs, Vcc drops to 2.7 V. The MCU's interrupt service routine time is 3055 - 1183 = 1872 μs, which is greater than the measured interrupt service routine time of 1350 μs; the EEPROM self-write valid time is 17869 - 3055 = 14814 μs, which fully meets the EEPROM write requirements. 4.4 Interrupt Service Routine To avoid the MCU frequently writing to the EEPROM and exceeding the maximum valid write count, the interrupt routine performs necessary filtering on the level of the interrupt input pin. The filtering algorithm is as follows: After the system enters the interrupt routine, it first disables interrupts, and then checks the level of INT0 10 times consecutively. If the level obtained by each check is low, the interrupt service routine continues to be executed. If it is high even once, the interrupt service routine immediately exits. After the data is written, it is necessary to ensure that the low level on INT0 is removed before returning to the interrupt; otherwise, it waits until the low level is removed. The interrupt service routine flowchart is shown in Figure 5. 5. Conclusion This paper details the design of the grating digital display system. The use of a CPLD significantly simplifies the system hardware design, reduces system costs, and enhances system reliability and flexibility. The selection of the STC89C516RD avoids the need for external memory expansion, thereby simplifying the design of the microcontroller's peripheral circuits.