Abstract: This paper designs an embedded DSP system access Ethernet hardware platform based on a digital signal processor (DSP) and a network controller. The network hierarchy architecture is simplified, and the corresponding network application software is designed, realizing the communication function between the embedded system and a computer via Ethernet. Keywords: Embedded system; Network interface; Digital signal processor 1. Introduction Combining DSP technology and computer network technology, integrating network technology into an embedded system based on a digital signal processor (DSP) facilitates the sharing of vast information resources in the interconnected network among various devices. This gives embedded devices unparalleled advantages in cost-effectiveness and real-time performance compared to general-purpose computers. Therefore, embedded DSP technology is increasingly widely used in network product development. Due to the broad application prospects of embedded network development, it has become a research hotspot. This paper utilizes a digital signal processor (DSP) and an Ethernet controller to construct an embedded intelligent Ethernet access platform, completing the hardware platform of an Ethernet embedded system based on a DSP. On this hardware platform, the embedded TCP/IP protocol is implemented, enabling the DSP embedded system to communicate and exchange data with a general-purpose computer via Ethernet. 2. Analysis of the Ethernet Controller The Ethernet controller primarily implements the functions of the Ethernet Media Access Control (MAC) layer and the physical layer, including MAC data frame transmission and reception, address identification, Cyclic Redundancy Check (CRC) encoding and verification, Manchester encoding, timeout retransmission, link integrity testing, and signal polarity monitoring and correction. The main processor only needs to read the received or transmitted frame data through the network controller's external bus. The internal block diagram of the Ethernet controller RTL8019AS is shown in Figure 1. [align=center]Figure 1 Internal Block Diagram of the RTL8019AS Network Controller[/align] The receiving logic, under the control of the receiving clock, concatenates serial data into bytes and sends them to the FIFO (First-In First-Out) and CRC. The transmitting logic, under the control of the transmitting clock, gradually shifts out bytes from the FIFO and sends them to the CRC. The CRC logic performs CRC verification on the input data during reception, compares the result with the CRC at the end of the frame, and if they are different, the data frame will be rejected. During transmission, the CRC generates a CRC for the frame data and appends it to the data tail for transmission. The address recognition logic compares the destination address of the received frame with the set local physical address. If they are different and not broadcast addresses, the data frame will be rejected. The FIFO logic buffers the transmitted and received data by 16 bytes to reduce the frequency of near-end DMA (Local Direct Memory Access) requests. The block diagram of the Ethernet controller DMA operation principle is shown in Figure 2. From the perspective of the master processor, the network controller can be regarded as a slave device that transmits and receives data to and from the Ethernet. Depending on the service target, the network controller can be divided into two parts: the remote DMA (Remote Direct Memory Access) channel and the local DMA (Local Direct Memory Access) channel. The remote DMA is mainly responsible for data exchange between the Ethernet controller's internal RAM and the main processor: the main processor performs data transmission and reception control operations on the network controller through read and write operations on the remote DMA. The local DMA is mainly responsible for automatically completing data exchange between the Ethernet controller and the network: when receiving data, the network controller stores the received data in its internal receive buffer; when a frame is full, it notifies the processor via an interrupt or register flag. When sending data, upon receiving a transmission command, the network controller automatically sends the data from the transmit buffer out in the standard frame format. [align=center] Figure 2 Block diagram of Ethernet controller DMA operation principle[/align] 3. Design of Network Interface Hardware Circuit The hardware interface circuit diagram between the DSP and the network controller RTL8019AS is shown in Figure 3. The network controller RTL8019AS is nominally powered by 5V, but actual testing has verified that the RTL8019AS chip can operate normally with a 3.3V power supply. The DSP chip TMS320VC5409 also operates at 3.3V, therefore the network controller's input/output can directly interface with the TMS320VC5409. [align=center] Figure 3: Hardware interface circuit diagram of DSP and network controller chip RTL8019AS[/align] The RTL8019AS locks the level of pin IOCS16 on the rising edge of reset. A high level indicates a 16-bit bus mode, and a low level indicates an 8-bit bus mode. For connection to an 8-bit master device, a 47kΩ pull-down resistor can be selected, with SD[8:15] left floating; for connection to a 16-bit master device, a 510Ω pull-up resistor can be selected. Since the RTL8019AS does not have an externally initialized EPROM, the I/O address of the command register (CR) is set to the default value of 0300H upon reset. Therefore, to meet the timing requirements of the RTL8019AS, the address connections A5 to A19 must lock the network controller's address at 0300H; otherwise, the main controller will be unable to access the registers of the RTL8019AS network controller. In this design, a 16-bit data bus is used to operate the network controller, mapping the network controller's address to the DSP's I/O space. The network controller registers are accessed via I/O. Therefore, the network controller address lines SA[0:4] need to be connected to the DSP chip address lines A[0:4]. The network controller address pins SA[8:9] are connected to a high level, and the address pins SA[10:19] are connected to a low level. The remaining control signal pins of the RTL8019AS network controller are directly connected to the CPLD. The DSP's logic control of the network controller is implemented through programming the CPLD. The network controller's network connection indicator (LEDBNC), network collision indicator (LED), receive indicator (LED1), and transmit indicator (LED2) pins are connected to LEDs to indicate the network controller's operating status. Since the input pins in the RTL8019AS chip are internally pulled down to ground by a 100K resistor, any floating pin in the chip is in a low-level state. 4. Network Software Design 4.1 Software Implementation Structure Network Protocol Layer Division The system refers to the ISO standard 7-layer OSI model. Based on actual application requirements, a reduced network software architecture can be adopted, as shown in Figure 4. The network architecture can be divided into three layers: the network data access driver control layer, the operating system control layer, and the user application data layer. The network data access driver control layer specifies the network topology and the electrical characteristics of data communication signals, implements point-to-point communication procedures, and fully executes the IEEE 802.3 CSMA/CD protocol; the operating system control layer integrates TCP/IP protocol suite components, completing the parsing of data obtained from the data link layer into data required by the user application; the user application data layer is responsible for data processing and analysis. [align=center]Figure 4 Network Software Architecture[/align] 4.2 Data Frame Structure Analysis The frame structure of the network control chip executing the IEEE 802.3 protocol is shown in Figure 5. [align=center]Figure 5 IEEE 802.3 Protocol Frame Structure[/align] The 62-bit preamble (PR) and 2-bit start-of-frame (SD) bits are automatically generated by the network control chip hardware as physical layer synchronization signals. The 48-bit destination IP physical address (DA) code indicates the destination physical address to which the data frame will reach, and the 48-bit source IP address (SA) code carries the source physical address of the data frame. The 16-bit TYPE/LEN code represents the data frame type or data frame length. The DATA segment contains the valid data for this type of packet, and the PAD padding segment is used to ensure that the minimum packet length of the data frame meets the IEEE 802.3 frame data structure requirement of not less than 60 bytes. The 32-bit hardware-generated automatic data check (FCS) segment performs parity checks on the transmitted data frames to ensure the correctness of the transmitted data. It is important to note the frame structure of the network controller RTL8019AS when receiving data packets, as shown in Figure 6. Comparing it to the IEEE 802.3 frame structure, it can be seen that the RTL8019AS adds a chip header to facilitate network driver development. This header includes the Receive State (RS) indicating the data reception status, the Next Page (NP) indicating the next page address, and the Frame Length (FL) indicating the total number of bytes in the received data frame. The addition of these three sections allows for better cooperation and coordination between the hardware and software. [align=center] Figure 6: Frame Structure of the Network Controller RTL8019AS[/align] 4.3 Data Frame Reception and Transmission Program Design The function of this system is to convert the encoded and compressed voice data from the embedded system into an Ethernet frame format, transmit it to the computer via Ethernet, and unpack the frame data received from the Ethernet, convert it back into the required voice data format, decode it, and output the voice data. Based on our simplified network software architecture, we designed the software hierarchically. The most crucial aspect is the design of the network control driver that interfaces with the operating system. This driver includes data sending and receiving operations, as shown in Figures 7 and 8. [align=center] Figure 7: Data Frame Sending Program Flow[/align] [align=center] Figure 8: Data Frame Receiving Program Flow[/align] 5. Conclusion This paper focuses on a DSP-based embedded Ethernet system. Based on the analysis of system requirements, an embedded network hardware platform was designed and implemented. The TCP/IP protocol software was developed on the embedded DSP system network hardware platform, enabling the embedded system to exchange data with the computer via Ethernet, ultimately realizing the embedded system's network function. The simplified network software architecture was used to design the software system, resulting in a small code size, a clear hierarchical structure, and ease of expansion and portability. The author's innovation lies in using a DSP and network controller to design and implement an embedded network application platform, providing a flowchart for reference in embedded applications. The overall design features a small code size, a clear hierarchical structure, and ease of expansion and portability. References: [1] Ma Zengqiang, Yan Yan, Yin Shishan. Railway crossing monitoring system based on DSP and Ethernet. Microcomputer Information [J], 2005, 7-2: 140-141 [2] Ye Kesong, Feng Tao, Wu Zifang. Application of peripheral interface technology based on DSP chip. Microcomputer Information [J], 2004, 5: 55-56 [3] Li Hongtao, Li Layuan. Design and implementation of broadband IP metropolitan area network. Journal of Wuhan University of Technology (Transportation Science and Engineering Edition) [J], 2003, 27 (2): 182-186 [4] Wu Xiaorong, Tu Shiliang. Implementation of Internet technology in embedded systems. Computer Engineering [J], 2001, 27 (4): 1-2 Author Biographies: Liu Xiaojie (1978-), male (Han nationality), from Gejiu, Yunnan Province, is a doctoral student at Jilin University, majoring in Communication and Information Systems, and his research focuses on digital signal processing and routing algorithms; Zhao Xiaohui (1957-), male (Manchu nationality), is a professor and doctoral supervisor at Jilin University, majoring in Communication and Information Systems, and his research focuses on signal processing theory and its applications in communication; Corresponding author: Gu Haijun (1970-), male (Han nationality), is an associate professor and master's supervisor at Jilin University, majoring in Communication and Information Systems, and his research focuses on digital signal processing and its embedded applications.