Abstract: This paper introduces a method for implementing a multi-serial port conversion gateway using an embedded system. Furthermore, it discusses in detail the microcontroller programming strategies, taking into account the characteristics and working principles of the C51F023 microcontroller and the MCF5272 processor.
Keywords: Embedded system; C51F023; MCF5272; Conversion gateway
introduction
In recent years, the Internet has become increasingly popular due to its convenience and high-speed data transmission capabilities. It has reached every corner of the world. However, in industrial control and communication equipment, serial port devices conforming to the RS-232 standard are still prevalent. How to forward data from multiple serial ports to the network to achieve remote control of equipment and remote data transmission has become a pressing problem. This paper proposes a scheme based on an embedded system to achieve data forwarding between serial ports and between serial ports and network ports.
Overall design scheme
The overall design scheme is shown in Figure 1.
Figure 1 Overall Design Scheme of Multi-Serial Port Conversion Gateway
This system adopts a two-tier design scheme consisting of a core processing module and a coprocessor. The purpose of this design is to use the coprocessor to alleviate the processing pressure on the core processor and to resolve the contradiction between the relatively insufficient number of data interfaces of the core processor and the system's requirement for multiple data access channels.
The core processor uses Motorola's MCF5272 chip. This chip is considered a mid-to-low-end product in Motorola's embedded processor lineup. However, low-end does not equate to low efficiency; at a clock speed of 66MHz, it achieves 63 MIPS, close to the MIPS of the MPC860. Furthermore, it boasts a rich array of peripheral interfaces, exhibiting the highest integration density among Motorola's ColdFire series chips. This processor integrates two full-duplex serial transceivers, a 10/100M Ethernet controller, a USB controller, a QSPI port, etc., making it ideal for numerous embedded applications. The core processor's peripheral expansion chips include FLASH, SDRAM, a network interface card (NIC) chip, and a USB driver chip. This forms a core processing module, on which we have ported the µCLinux operating system. Utilizing the built-in TCP/IP protocol stack in µCLinux, network data transmission and reception can be easily implemented.
The coprocessor uses the CYGNAL C8051F023 microcontroller. The C8051F023 microcontroller has two built-in general-purpose asynchronous full-duplex serial ports and one SPI port. A third full-duplex serial port can be simulated in software using the microcontroller's internal PCA module. The coprocessor and core processor connect via the synchronous serial interface SPI for data exchange. Data is continuously received from the three serial ports on the microcontroller side, processed uniformly, and then transmitted to the MCF5272 via the SPI line. The core processing module receives data frames from the SPI line and its own two serial ports, and performs store-and-forward operations based on the flag bits in the data frame header. The entire system has five full-duplex serial ports and one 10/100M Ethernet port for data transmission and reception, enabling data forwarding between serial ports and between serial ports and Ethernet ports. This meets the needs of most industrial control equipment and communication systems.
Implementation of multi-task scheduling in microcontrollers
The C8051F023 microcontroller needs to implement full-duplex transmission and reception of three serial ports and communication with the MCF5272. There are two approaches to achieving this functionality: one is to periodically poll specific registers of each serial port and SPI port to determine if data has arrived and process it accordingly. This approach is simple to program but has poor real-time performance. The other approach is to use an interrupt mechanism, defining interrupt vectors and interrupt handlers for each serial port. This approach is more complex to program but offers excellent real-time performance. Based on our requirements, the transmission and reception of data through the serial ports, the SPI port, and the execution of the internal program timer are all tasks that require real-time operation. Therefore, the second approach provides better real-time performance. Since the microcontroller does not have an embedded operating system, these multiple tasks must be implemented using a multi-interrupt strategy combined with synchronization locks.
Hardware serial ports, SPI ports, and timers each have their own interrupt vectors and interrupt handler modules, while software serial ports rely on custom external interrupt vectors to implement the interrupt mechanism for receiving and transmitting. These interrupts all have the same interrupt level. If an interrupt conflict occurs, the interrupt handler with the smaller interrupt vector number is executed first, followed by the interrupt handler with the larger interrupt vector number, according to the 51 microcontroller's interrupt vector table.
If new data is received and enters the transmit buffer simultaneously with the transmitted data, unavoidable communication errors will occur. Such problems require a synchronization lock to solve. Considering real-time effects, the mechanism for implementing the C8051F023 synchronization lock is as follows: when a data frame to be transmitted enters the transmit buffer, the interrupt handler immediately locks it, preventing new data from entering the transmit buffer until the entire frame has been transmitted, at which point the lock is released, and new data is then allowed to enter the transmit buffer. Simultaneously, four secondary buffers are partitioned internally within the microcontroller to store data received from the three serial ports and one SPI port, preventing data loss.
Connection and communication between microcontroller and MCF5272
The microcontroller communicates with the MCF5272 via the SPI interface. The hardware circuit is shown in Figure 2.
Figure 2 shows the connection diagram between the microcontroller and the MCF5272.
SPI is a synchronous serial interface, requiring synchronous transmission and reception. However, in practical applications, the reception of command signals and the transmission of data from various serial ports are obviously asynchronous. This necessitates asynchronous programming design for the SPI port.
The MCF5272's QSPI port is set to master mode, acting as the transmitter of the SPI clock; while the microcontroller's SPI port is set to slave mode. During program execution, the MCF5272 continuously sends data through the QSPI port, sending "0" data when not sending command frame data. The microcontroller's SPI port continuously receives data, discarding the "0" data and receiving useful command frame data from the MCF5272. Due to the synchronous transmission and reception characteristics of SPI, the MCF5272 can continuously receive data from the microcontroller's SPI port while continuously sending data. Similarly, after discarding meaningless "0" data, it will receive various different data transmitted through various serial ports. This achieves the transformation of the synchronous SPI port into asynchronous full-duplex operation.
Data frame standardization
Data received from the microcontroller's three serial ports will be transmitted to the core processor MCF5272 via the SPI interface, while data from the core processor will also be transmitted to the microcontroller via the SPI port. This necessitates a consistent data interface between the microcontroller and the MCF5272 to facilitate data distribution and reception. We need to redefine the frame format for the data frames received from the three serial ports and from the SPI port, performing standardization processing. The standardized frame format is shown in Figure 3, where the serial port source address identifies which serial port the data originates from, and the serial port destination address identifies which serial port the data will be sent to.
Figure 3. Serial port data frame transmission format
On the MCF5272 core processing board, data received from the serial port and forwarded to the network also needs to undergo homogenization processing. The frame format is shown in Figure 4.
Figure 4. Network port data frame transmission format
Conclusion
The five full-duplex serial ports and one Ethernet port of the entire system are completely transparent to the core processing board. Only upper-layer application software needs to be written under µCLinux according to the specific requirements of the actual situation, making it suitable for most industrial control and communication equipment. If a wireless transmission module is connected at the back end, this solution is also applicable to wireless communication.
References:
1. *C8051F020/1/2/3 Mixed-Signal ISP FLASH Microcontroller Datasheet*, translated by Pan Zhuojin. 2. *MCF5272 Coldfire Integrated Microprocessor User's Manual* 3. *8051 Microcontroller C Language Control and Application*, edited by Chen Longsan, Tsinghua University Press.
