Abstract: This paper introduces the structure of a DSP embedded multimedia system based on PCI bus, focuses on the hardware structure of the DSP system board in the system, and briefly describes the application prospects of the system. Keywords: PCI bus, DSP, multimedia embedded system 1 Introduction Since Intel first proposed the concept of PCI bus in 1991, this high-performance bus has become a very mature bus structure after more than ten years of development and is used in high-speed peripheral devices including sound cards, network cards and graphics cards. It operates at a clock frequency of 33MHz and works at a peak transmission rate of 132MB/s under a 32-bit data bus. The PCI specification version 2.2 released in 1999 supports a 66MHz main frequency and a 64-bit data path, with a peak transmission rate of up to 528MB/s, which is suitable for voice, graphics, image processing and other high-speed peripherals that require high-speed data transmission [1][5]. On the other hand, the development of DSP is also extremely rapid. After launching its first fixed-point DSP-TMS32010 chip series in 1982, TI has successively launched six generations of fixed-point DSP chip series [2]. The on-chip resources are becoming richer and richer, the processing power is increasing by dozens of times, and the processing speed is increasing from the initial 5MIPS to more than 100MIPS. It is widely used in signal processing, communication, voice, image and military fields. For embedded systems, the core is an embedded microprocessor with data processing and system management capabilities. This microprocessor must have strong support for real-time multitasking. Therefore, by giving full play to the advantages of DSP devices in data processing and speed, and forming an embedded system, the real-time operation characteristics of the embedded system can be improved [4]. Using the PCI bus as the overall organizational structure of the system can solve the bottleneck problem in data transmission and improve the real-time data processing capability. 2 System Structure The structure of this system is similar to that of a PC system, as shown in Figure 1. It consists of a baseboard and multiple PCI cards. The difference between it and the PC system is that its processor is not directly plugged into the motherboard, but appears as a PCI card system board. The system uses 10M/100M compatible PCI network cards. Multiple embedded systems form a 100M local area network (LAN) through a shared hub and a 100M switch. The sound card is used for voice data acquisition and playback of audio data transmitted from the network. Dynamic image compression data transmitted from the network is decompressed by the DSP system board and transmitted to the graphics card via the PCI bus. The graphics card connects to the monitor for dynamic image display. The system backplane serves not only as a support bracket but also provides a 33MHz PCI synchronous clock for each PCI device. Since the PCI bus is a synchronous bus, all operations on the PCI bus must be synchronized with the PCI clock signal. Therefore, the 33MHz PCI clock signal provided on the backplane must provide timing for all PCI bus transactions, including bus arbitration. However, the crystal oscillator has limited driving capability, requiring an additional clock drive circuit. [align=center] Figure 1 System Structure Diagram[/align] Another important function of the baseboard is to provide a PCI bus arbiter. The arbiter responds to the bus usage requests made by various multimedia devices and coordinates the operation of each device on the bus, so as not to generate bus conflicts and excessive bus delays, thereby realizing high-speed PCI bus transmission[5]. The PCI bus arbiter can be implemented by a CPLD. In addition, some pull-up resistors for control signals should be provided on the baseboard to prevent excessive current from being generated on the control bus when there are no devices driving it. 3 DSP System Board Hardware Structure As the core processing unit of the entire DSP embedded system, the system board also exists in the system in the form of a PCI card. The system board is connected to the PCI bus through the PCI interface chip. Its function is to control the data transmission and storage between various multimedia devices. Among them, the PCI interface chip uses PCI9054, which has the following functions [6]: ● Supports PCI specification version 2.2; ● Has master device function, supporting local bus processor to access other devices on the PCI bus; ● Local bus mode is programmable (M, C, J modes), local bus clock frequency can reach up to 50MHz; the transmission rate between local bus and PCI bus can reach up to 132MB/s; ● Has 6 zero-wait-state FIFOs for burst transmission; ● Dual independent scatter/gather DMA channels with programmable FIFOs; ● Has programmable PCI interrupt and local bus interrupt output. PCI9054 is used to connect DSP and PCI bus. It works in C mode with 32-bit data and 32-bit address non-data address multiplexing, and controls the data transmission method between DSP and other devices on PCI bus. These transmission methods include PCI start mode, PCI destination mode and DMA mode. The PCI start mode allows the PCI9054 to execute memory operation cycles, I/O operation cycles, and configuration cycles on the PCI bus. It allows the processor on the local bus to access the registers inside the interface chip and access other devices on the bus through the interface chip. The PCI target mode allows other master devices on the PCI bus to access the PCI9054's local bus. In this mode, the interface chip acts as both the target device on the PCI bus and the master device on the local bus. The PCI9054 also has two DMA channels. Channel 1 can operate in command mode, block mode, and distributed aggregation mode, while channel 2 can operate in block mode and distributed aggregation mode. The distributed aggregation DMA controller allows for efficient management of multi-channel data transfer between the PCI bus and the local bus with minimal software intervention. The DSP can be the 16-bit fixed-point DSP TMS320VC5409 from TI. This DSP chip has the following main features [8]: ● The fastest fixed-point single-cycle execution time can reach 10ns (100MIPS); ● Advanced multi-bus interface with 3 independent 16-bit data memory buses and 1 program memory bus; ● In extended address mode, it can reach a maximum external program address space of 8M*16bit; ● It has 16k*16bit on-chip ROM and 32k*16bit on-chip DARAM, both of which can be configured as data memory or program memory through registers and chip pins; ● Enhanced 8-bit host interface (HPI16) with 16-bit on-chip data address bus; ● 6-channel DMA controller. The hardware structure of the DSP system board is shown in Figure 2: [align=center] Figure 2 DSP system board structure[/align] The PCI9054 is connected to the DSP's 16-bit host interface (HPI16) [7]. The DSP's 16-bit host interface enables the host (in this system, PCI9054) to access all on-chip RAM of the DSP through the DMA bus. In this way, other devices on the PCI bus can access the RAM space inside the DSP through PCI target mode. The PCI9054 and the DSP can transmit non-multiplexed 16-bit addresses and data. Both parties can generate interrupt signals during data transmission. The host accesses the 32k DARAM inside the DSP chip through three HPI registers. When the host wants to read the data of a certain address of the DSP's DARAM, it writes this address to the HPI address register (HPIA) and then reads the contents of the HPI data register (HPID). When the host writes to the DSP's on-chip space, it first writes the address to HPIA and then writes the data to HPI to complete the process. HPIC is the HPI control register, used to store the control bits and status bits of HPI [3][8]. In Figure 2, the serial E2PROM is used to initialize the configuration registers inside the PCI9054. After the system powers on, the PCI9054 reads the E2PROM and writes the corresponding data into the configuration registers to complete the initialization. High-speed SRAM is used as a high-speed program memory when the DSP is running offline. This is essential to fully utilize the DSP's high-speed advantage. If the DSP's program memory speed is slow, the DSP will need to wait during instruction fetching, limiting the speed of DSP instruction execution. FLASH program memory is also used to store the DSP's program. Its function differs from high-speed SRAM in that FLASH temporarily stores program code before the DSP program runs. Because the DSP selected in this system only has an internal mask ROM as its program memory, although the internal RAM can be used as program memory, it only has 32KB of words. Therefore, the bootloader in the DSP's internal mask ROM is needed to transfer the user boot program to the DSP's internal RAM via the DSP's general-purpose serial port. The user bootloader's role is to transfer the program code stored in FLASH to the high-speed SRAM and then begin execution. In the diagram, the CPLD serves two main functions. Firstly, it acts as a decoding circuit between the local bus of the PCI interface chip and the host interface of the DSP. Essentially, it acts as an arbitrator for the PCI local bus, arbitrating requests from the PCI interface chip and the DSP to occupy the local bus, coordinating their logical relationships, and ensuring smooth operations on the local bus. Secondly, the CPLD also functions as a decoding circuit between the DSP and the FLASH program memory. Since FLASH access speed is relatively slow, the DSP needs to apply a suitable waiting state to successfully read program code from FLASH into SRAM. 4. System Application Prospects This 100Mbps LAN, composed of a multimedia embedded system based on the DSP and PCI bus, serves as a basic high-performance real-time communication network platform. Its bandwidth fully meets the requirements for transmitting dynamic image and voice compressed data, making it suitable for multimedia fully digital language learning systems. Because such learning systems are still relatively rare, and products based on the DSP and PCI bus with video functionality have not yet appeared, this learning system has a very promising market prospect. Furthermore, this multimedia embedded system has a wider range of applications, playing a direct role in video conferencing systems, video-on-demand systems, high-speed distributed data acquisition systems, and many other fields, including military information systems. References [1] Tom Shanley, Don Anderson. PCI System Architecture (Fouth Edition). Publishing House of Electronics Industry. July 2000 [2] PCI 9054 Data Book v2.1. PLX Technology Inc. January 2000 [3] Texas Instruments TMS320VC5409/21 DSP to PCI Bus Application Note. PLX Technology Inc. June 2000 [4] TMS320VC5409 Data Book. Texas Instruments Incorporated. 2000 [5] Li Guishan, Qi Dehu. PCI Local Bus Developer Guide. Xi'an: Xi'an University of Electronic Science and Technology Press, 1997 [6] Dai Mingzhen, Zhou Jianjiang. TMS320C54x DSP Structure, Principle and Application. Beijing: Beijing University of Aeronautics and Astronautics Press, 2001 [7] Huang Xun. Design of DSP Data Operation Platform Based on PCI Bus. Electronics World, 2001, Issue 5, Page A [8] Li Zheying, Luo Li, Liu Yuansheng. Embedded system technology with DSP devices as the core. Electronics World, 2001, Issue 5, Page A