This paper introduces a master-slave communication method for RS485 communication bus, which improves the acquisition speed of RS485 bus. This method solves the problem of slow master-slave communication, improves communication speed, and is stable and reliable in operation.
introduction
Industrial sites frequently require the collection of multi-point data, including analog or switching signals. This typically utilizes an RS485 bus with a master-slave communication model. This method is convenient, requiring only two shielded cables, and offers a long communication distance of up to 1500 meters, which can be extended with repeaters. The differential signaling method provides good electromagnetic interference immunity. However, this method has limitations in communication speed. It generally employs a master-slave call mechanism to collect data from each sub-unit, where the master unit sequentially calls each sub-unit (see Figure 1). The unit that is called uploads data, and the master unit allocates all bus usage rights; sub-units cannot unilaterally occupy the bus. If the system has many units, the master unit's cycle time for data collection can be very long, and changes in sub-unit information cannot be promptly transmitted to the master unit, resulting in slow system response to sudden events. This paper addresses this issue by implementing bus status detection and active slave data transmission.
Figure 1. Interface diagram of conventional RS485 bus master-slave mode
Hardware Design
The entire system consists of a main unit and multiple sub-units (Figure 2). The main unit includes: an ARM7 microcontroller, program memory, data memory, RS485 communication with sub-units, RS485 communication with the main unit, system power supply, and communication isolation power supply; the sub-units include: an MSP430 microcontroller, RS485 communication with sub-units, system power supply, and communication isolation power supply.
Figure 2 System Block Diagram
Main unit
The ARM microcontroller is the core of the main unit, using the Samsung 32-bit ARM7TDMI core chip S3C44B0. This chip has a maximum processing speed of 76MHz, an open bus, and can be expanded with external program memory FLASH and data memory SDRAM. The system expands with SST's 39VF1601 and Hyundai's HY57V641620HG, and has two UART serial interfaces. It uses ADI's isolated RS485 chip ADM2483 for interface level conversion, and the bus status detection uses the 74HC125 tri-state gate chip.
subunit
The sub-unit uses TI's MSP430F133 microcontroller, which has a processing speed of up to 8MHz, 8K bytes of on-chip FLASH storage, and 256K bytes of on-chip SRAM.
Power supply circuit
The power supply circuit uses a switching power supply, which has a wide input voltage range and an output DC voltage of 5V. A 3.3V power supply is output through SP1117-3.3 and SP1117-2.5 chips. The isolated 5V power supply required by RS485 is obtained through a DC-DC module.
Bus detection circuit
Bus status detection uses a 74HC125 tri-state gate chip and two I/O pins of the microcontroller (Figure 3). When the system is not using the bus, each unit's 74HC125 outputs a high-impedance state, and the bus is low. When a unit wants to use the bus, it first checks the bus status. If the bus is low, the unit quickly changes the 74HC125 to the output state, and the bus becomes high. The unit then occupies the bus and sends data to it. After sending the data, it changes the 74HC125 back to the high-impedance state. If the bus is detected to be high, the unit waits for detection until the bus goes low before occupying the bus.
Figure 3 Bus detection circuit
Isolated 485 circuit
The interface level conversion is performed using the ADI ADM2483 chip (Figure 4). This chip is an isolated 485, with dual power supply and isolated input and output.
Figure 4. Isolated 485 circuit
Software Design
The host program needs to implement the reception, processing, and uploading of data from each slave device. The host receives information from the slave units via an RS485 serial port. The data format is hexadecimal, with 8 data bits, one start bit, one stop bit, no parity bit, and a baud rate of 9600bps. Serial port interrupts are used for reception. After the host program initializes, it waits for information to be sent by each slave device. When the host receives the first byte, it checks if the byte is the device number. If not, the receive count is reset to zero; if it is, it continues receiving the second byte. It then checks if the second byte is the correct function code. If the function code is incorrect, the receive count is reset to zero and reception is restarted. If the function code is correct, the host receives the third byte, which represents the number of bytes (x) sent by the slave unit. The total number of bytes sent by the slave unit is calculated as M = X + 3 + 2, including 3 start bytes and 2 CRC checksums. After receiving M bytes, the host first checks if the CRC checksum is correct. If incorrect, all information is discarded; otherwise, the slave unit's information is saved to the data area, and the reception ends. The host then continues waiting for further reception.
Information is uploaded via an RS232 serial port. When the host receives information from the slave device, it processes the data and detects a change in the slave device information. The host then prepares to send the slave device information to the host computer. First, it reinitializes the transmit buffer, and then sends the information to the host computer sequentially via interrupt. The transmitted information includes the device number, function code, number of bytes to be transmitted, information bytes, and CRC checksum.
The data receiving process of the host unit is illustrated in Figure 5.
Figure 5 Program Flowchart
Conclusion
The system designed by the author realizes multi-point monitoring of switch signals, with one master unit and 32 slave units. Each slave unit monitors 32 switches, and the system can monitor a total of 1024 switches using a baud rate of 9600bps. Using a master-slave call method, the response time for switch signal monitoring is typically 20-30 seconds. Using this bus detection method, the response speed is at least 1 second, and sometimes only a few hundred milliseconds, greatly improving the response time. Furthermore, because it does not require constant calling, the bus data flow is reduced, improving bus stability.
References:
1. Li Chaoqing, PC and Microcontroller Data Communication Technology, Beijing University of Aeronautics and Astronautics Press
2. Tian Ze, Embedded System Development and Application, Beijing University of Aeronautics and Astronautics Press.
