Abstract: PC/104 bus computers used for field control in control systems often need to communicate with multiple nodes in various ways. This paper introduces a method for developing a multifunctional, universal extended communication module with four serial ports (two RS-232 and two RS-485) and a CAN bus interface according to the PC/104 standard. In the design, all control logic is implemented by a single CPLD, and the timing between the CAN controller and the 104 bus is also adjusted by the CPLD. Keywords: PC/104 bus, CAN bus, CPLD, multi-serial ports Abstract: This paper presents the design and realization of a communication module with 4 serial ports and a CAN bus interface. It is based on the PC/104 standard. All control logic in the module is executed by a CPLD device. The time sequence between the 104 bus and the CAN controller is also adjusted by the CPLD. Key words: PC/104 bus, CAN bus, CPLD, Multi-serial ports 1 Introduction PC/104 bus computers are characterized by small size, low power consumption, wide operating temperature range, and high reliability, and are widely used in distributed systems and distributed control systems as field control computers. In these systems, the 104PC often needs to communicate with the host computer and the connected control actuators, sensors, or measuring instruments. Common communication methods include RS-232 serial port with MODEM, RS-485, Ethernet, and various industrial fieldbuses. RS-232 serial port with modem is generally used for long-distance point-to-point data transmission; RS-485 is generally used for multi-point control in the field and remains the most widely used method in industrial control; Ethernet can achieve remote control and information sharing, but its latency is uncontrollable, limiting its application in control systems with high real-time and security requirements; Fieldbus technology is one of the hottest developments in the field of automation today. It is a system used in control fields to achieve bidirectional serial multi-node digital communication between microcomputer-based measuring devices, and is also known as an open, digital, multi-point communication underlying control network. There are many fieldbus standards, among which CAN bus has developed the fastest in China and is considered one of the most ideal alternatives to RS-485. The CAN bus specification has been established as an international standard by ISO. Its model structure has three layers, including the OSI physical layer, data link layer, and application layer. The maximum communication rate can reach 1Mbps/40m, the maximum direct transmission distance can reach 10km/5Kbps, and the maximum number of devices that can be connected can reach 110. The electrical specifications of the CAN bus are similar to RS-485, employing two-wire differential balanced transmission. Digital logic is represented by the voltage difference between the two lines, and is divided into "dominant" and "recessive" logic. The CAN bus uses a content-oriented addressing scheme, allowing new stations to be added without hardware or software modifications. Data is transmitted in messages, with message priority combined in an 11-bit identifier, ensuring that data with different real-time requirements is transmitted with different priorities. Conflicts during bus reads are resolved through bit arbitration. The CAN protocol uses five error-checking methods to guarantee data transmission reliability. The CAN bus offers low cost, high real-time processing capabilities, and reliable operation even in harsh environments with strong electromagnetic interference. In summary, based on the current application characteristics and requirements of the 104PC in industrial control, the purpose of this design is to design a general-purpose, multi-functional extended communication module according to the PC/104 standard. This module includes two RS-232 serial ports, two RS-485 interfaces, and one CAN bus interface. 2. Component Selection and Overall Design Scheme To expand the communication module with four serial ports and one CAN bus interface according to the PC/104 standard, strict limitations were placed on module power consumption and size. Therefore, highly integrated ICs were required. The asynchronous communication unit is the core component for serial port expansion. It performs the conversion between parallel and serial data and completes the corresponding control at a specified baud rate and data format. The design selected TI's highly integrated asynchronous communication control unit TL16C554 chip, which integrates four ACEs (Asynchronous Communication Units), sharing data lines and some logic control signals. Each ACE unit can be selected via its own chip select signal. Each transceiver unit has its own interrupt request, data transmission and reception, and MODEM logic control signals, enabling it to perform all the functions of an asynchronous transceiver. RS-232C to TTL level conversion is performed using the Max213. The Max213 uses an SSOP package, has a small size and low power consumption; one Max213 plus a few small capacitors can complete the level conversion of all signals in a standard RS-232C transceiver. The RS-485 to TTL level conversion is achieved using the SN65LBC184. The SN65LBC184 is an RS-485 bus driver chip from Texas Instruments, featuring a simple structure, low power consumption, and single-chip implementation of half-duplex RS-485 communication. It employs a 1/2 load design, allowing 64 units to be connected on the bus, and also features anti-static, surge protection, and overheat protection, improving system reliability. The CAN bus controller is the core device for expanding the CAN bus interface. It forwards parallel data from the ISA bus on the 104PC according to the CAN bus protocol, and simultaneously receives data from external buses according to the CAN bus protocol. The PHILIPS SJA1000 independent CAN bus controller was selected in this design. The SJA1000 is an upgrade of the PCA82C200, integrating the CAN bus logic link layer protocol. It is fully compatible with the PCA82C200 in both hardware and software, and also features a PELI operating mode (supporting the CAN 2.0B protocol) that supports extended CAN bus protocols. Specifically, the SJA1000 features an extended 64-byte FIFO receive buffer, support for 11-bit and 29-bit identifier codes, support for standard and extended frame information transmission, and numerous PELICAN mode extension functions such as single/double mask filters, arbitration loss interrupt, listen-only mode, self-information reception, and recent error register. CAN bus level to TTL level conversion is handled by the PHILIPS PCA82C250. This chip is ISO11898 compliant, supports high-speed transmission up to 1 Mbaud, and can connect up to 110 nodes. It employs slope limiting control to reduce RF interference and has a wide range of common-mode interference and electromagnetic interference immunity. The logic and timing control involved in the design are implemented using a CPLD. This is primarily due to the following considerations: • Using discrete components such as NAND gates, decoders, and latches for logic control would make it difficult to arrange numerous components on the PCB, complicate the circuit, and reduce the module's reliability and anti-interference capabilities. The SJA1000 CAN controller uses a time-division multiplexed address/data interface, while the PC104 lacks this feature. Therefore, timing conversion is necessary to establish a connection. Currently, the common approach is to use an 8031 ​​microcontroller for data forwarding: the 8031 ​​connects to the CAN controller, and the PC104 directly transmits data to the 8031 ​​via I/O ports, or writes data to a dual-port RAM, which the 8031 ​​then reads from another port and uses to operate the CAN bus controller to forward the data. This method undoubtedly increases the complexity of the components and circuitry. To address this, a method using a CPLD to integrate timing signals for the connection between the PC104 and the CAN controller was designed. The PC104 sends out the operation address and data in a time-division multiplexed manner, and the CPLD integrates the relevant logic control signals to meet the timing requirements of the CAN controller. Using a CPLD allows for the definition of input/output pins as needed, facilitating PCB layout and routing. Furthermore, using a CPLD eliminates concerns about the types and quantities of components used in the design, allowing for the definition of any required components and thus optimizing circuit performance. • Using a CPLD allows for software simulation of the circuit, facilitating circuit debugging. • Using a CPLD allows for online modification of its internal logic, enabling upgrades or bug fixes without altering the external circuitry. The CPLD chip selected is the ALTERA EPM7064SLC84-10, which features a second-generation MAX structure based on EEPROM and supports in-system programming via JTAG pins. It has 64 macrocells, 4 logic array blocks, 1250 available gate units, supports 5V/3.3V multi-voltage I/O interfaces, and provides 68 user I/O pins. Based on the above scheme, the structure of the communication expansion module is shown in Figure 1. [align=center] Figure 1 Structure of the expanded communication module[/align] 3 Hardware Implementation 3.1 Address Decoding Circuit This expansion module requires a total of seven I/O addresses, with two I/O addresses for the CAN controller, four I/O addresses for the four serial asynchronous communication units, and one I/O address for the interrupt sharing circuit. I/O addresses must be selected appropriately; otherwise, unpredictable system conflicts may occur. The I/O address allocation for various PC104 computers is generally the same. Taking the Shengbo SysCenterModule/SuperDx as an example, addresses 110H to 140H are selected as the I/O addresses for the extended communication module. The address allocation is shown in Table 1, and the logical decoding structure is shown in Figure 2. Table 1 I/O Address Allocation Table [align=center] Figure 2 I/O Address Logical Decoding Structure[/align] Figure 2 can be easily implemented using VHDL. The specific description is as follows: SEL(0)<=AEN; SEL(1)<=NIOW AND NIOR; SEL(2)<=ADDR(0); SEL(3)<=ADDR(1); SEL(4)<=ADDR(2); SEL(5)<=ADDR(3); SEL(6)<=ADDR(4); SEL(7)<=ADDR(5); SEL(8)<=ADDR(6); WITH SEL SELECT Y<="1111110" WHEN "010001000",//IO/110 Address operation "1111101" WHEN "010001100",//IO/118 Data operation "1111011" WHEN "010010000",//IO/120 Serial port 1 "1110111" WHEN "010010100",//IO/128 Serial Port 2 "1101111" WHEN "010011000",//IO/130 Serial Port 3 "1011111" WHEN "010011100",//IO/138 Serial Port 4 "0111111" WHEN "010100000",//IO/140 Read Interrupt Number "1111111" WHEN OTHERS; END BLOCK CODE; 3.2 Interface between 104 Bus and CAN Controller As mentioned above, the 104 bus is compatible with the ISA bus but has different timing requirements than the CAN controller. In this design, the BALE, address, and read/write signals in the 104 bus are integrated by the CPLD logic and provided to the CAN controller. At the same time, the operation address and operand are sent out from the data line in a time-division multiplexing manner to meet the timing requirements of the CAN controller. The timing-integrated VHDL language is as follows: ALE<=（NOT Y（0）） AND BALE; CSCAN<=Y（1）; IORCAN<=Y（1） OR NIOR; IOWCAN<=Y（1） OR NIOW; The VHDL implementation of bidirectional data buffer can be found in many reference books, and is omitted here. 3.3 Asynchronous Communication Interface Circuit and Interrupt Sharing Circuit The interface of 16554 can be seamlessly connected with PC104. The CPLD implements the selection and read/write logic control. The asynchronous communication and CAN controller share the bidirectional data buffer circuit in the CPLD. The asynchronous communication control unit 16554 has strong interrupt capability. The four serial controllers have their own interrupt pins, which are flexible to use. However, the interrupt resources of the system are limited. If each controller occupies an interrupt number, the communication module needs to occupy five interrupt numbers. In order to save interrupt resources, the four serial port controllers share one interrupt in the design, while the CAN bus controller occupies one interrupt separately. In order to achieve sharing, an interrupt vector register is set up. When an interrupt occurs, the interrupt vector register is read first to locate the serial port that issued the interrupt. The principle is shown in Figure 3. [align=center] Figure 3 Interrupt Sharing Circuit[/align] The VHDL language implementation is as follows: GMID<=NIOR OR Y (6); INTSER<=INTABCD (0) OR INTABCD (1) OR INTABCD (2) OR INTABCD (3); INTID<=INTABCD WHEN (GMID='0') ELSE "ZZZZ" 4 Conclusion This design utilizes CPLD to realize the timing conversion between the 104 bus and the CAN controller, the logic control of the entire circuit, and interrupt sharing, making the circuit design compact and stable. The 104PC, which expands the RS-232, RS-485, and CAN interfaces, can meet the communication requirements of most control systems. This design has been adopted by a distributed air defense system, and the performance indicators have met the requirements in all joint debugging tests. References: 1. SBS Science & Technology Co., Ltd. PC/104 Technical Manual. 2000. 2. Altera. MAX 7000 Programmable Logic Device Family Data Sheet. 1995. 3. Texas Instruments. TL16C554 Asynchronous Communication Element Data Sheet. 1998. 4. Philips Semiconductors. SJA1000 Stand-alone CAN Controller data sheet. 1997.