Abstract: This paper introduces a high-quality variable frequency power supply. Its rectifier employs APFC technology, and the inverter uses phase-locked loop (PLL) frequency tracking technology, improving the power factor of both input and output. This is of great significance for the effective operation of the power grid, the variable frequency power supply, and the load. Keywords: Active power factor correction; Phase-locked loop; Frequency tracking; Variable frequency power supply 1. Circuit Structure and Working Principle The main circuit structure of the new variable frequency power supply is shown in Figure 1. D1-D4 are conventional rectifiers, S1-S4 are conventional inverters, and S5 and D5 are Boost choppers. When the conventional rectifier is combined with the Boost chopper boost circuit and controlled by APFC technology, a rectifier with a high input power factor is formed. When the inverter is combined with the PLL circuit and controlled by frequency tracking technology, a high-quality variable frequency power supply is formed. S1-S4 and S5 use a new generation of power electronic devices, power MOSFETs, which have high operating frequency and large power capacity. When operating in switching mode, under ZCS or ZVS conditions, the losses are low and the operation is reliable. Alternating current (AC) is rectified and filtered to form direct current (DC). This DC then passes through an APFC (Analog-Pulse-Controlled Current) circuit, where its current and voltage loops regulate the input current to track the voltage waveform and phase, thereby improving the input power factor and achieving voltage regulation/stabilization. The inverter converts this DC voltage into an alternating voltage with a frequency matching the load's (or transducer's) resonant frequency. A current sampling circuit sends the current signal to a phase-locked loop (PLL) to track the operating frequency, obtaining a corresponding frequency signal. This signal is then passed through a drive circuit to generate a drive signal. A phase compensation circuit adds compensation time to the drive signal, forming a PWM (Pulse Width Modulation) waveform. Finally, after isolation by a pulse transformer, this PWM signal serves as the control signal for the switches on the inverter bridge arms, ensuring correct on/off switching and forming a closed-loop frequency control circuit. 2. Rectifier Design Based on APFC Technology The main circuit of the APFC-based rectifier adopts a Boost converter structure, as shown in the dashed box in Figure 1. The core of APFC technology is the introduction of voltage and current feedback to form a dual closed-loop control system. The outer loop stabilizes the output voltage, while the inner loop regulates and shapes the input current to create a standard sine wave in phase with the voltage, thus improving the input power factor. The inner-loop current control continuously regulates the input current, ensuring the grid supplies current to the rectifier throughout the entire cycle. The APFC rectifier using the UC3854 is shown in Figure 3. Pins 5 and 4 of the UC3854 are connected to the current sampling resistor R18 in the main circuit via resistors (R4 and R3). Pin 11 is connected to the output of the APFC main circuit. Pin 6 inputs the line voltage waveform, and pin 8 inputs the effective value of the line voltage. After processing by the UC3854, a PWM signal is obtained at pin 16 to control the MOSFET (S5) switch. The current sampling at pins 5 and 4 of the UC3854, the rectified voltage waveform at pin 6, the PWM drive at pin 16, and the MOSFET (S5) switch form a closed-loop current regulator within the UC3854; the regulation results in the main circuit current tracking the rectified voltage waveform. The voltage sampling and rectified voltage RMS value circuit connected to pin 11 of the UC3854, along with the PWM drive circuit on pin 16, form a closed-loop voltage regulator inside the UC3854, enabling the APFC rectifier to output a highly stable DC voltage. The APFC rectifier also incorporates a protection circuit. When pin 10 of the UC3854 is connected to a high level, the control circuit operates. The chip's operating voltage is 17V to 22V, and a Zener diode is connected to pin 15 for voltage limiting protection. A capacitor is connected to pin 13 to implement a soft-start function, and the circuit at pin 2 is used to limit the maximum current. Analysis of the component parameters and dual closed-loop circuitry in the APFC circuit can be found in references [2, 3]. Experiments show that the input current and voltage waveforms are in phase, and the power factor is above 0.98. 3. Inverter Design Based on Frequency Tracking Technology When the inverter is operating, the MOSFET switches switch according to the resonant frequency of the load (or transducer), as shown in Figure 1. S1, S4 and S2, S3 form two sets of switches respectively. These two sets of switches are turned on alternately, and the switches switch when the current in the load crosses zero. When the inverter's operating frequency is equal to the resonant frequency of the load (or transducer), the circuit output voltage is a square wave and the output current is a sine wave, as shown in Figure 1(b). The circuit adopts a zero-current switching mode, which has extremely low switching losses, greatly reduces the du/dt and di/dt stresses, and eliminates the corresponding electromagnetic interference. 3.1 Frequency Tracking Control Circuit The CD4046 integrated phase-locked loop can realize frequency tracking control without phase difference. The load voltage or current phase is used as the input signal of the phase-locked loop, and the output of the phase-locked loop is used as the drive signal of the inverter to realize the inverter's frequency tracking of the load. The control circuit is shown in Figure 4. The sinusoidal load current signal detected by the Hall current sensor is shaped into a square wave signal by the comparator LM339 and sent to pin 14 of the CD4046 phase-locked loop. After frequency tracking control, the signal is output from pins 3 and 4, which is then processed by the drive circuit to form a PWM drive waveform for the MOSFET. Finally, after isolation by the pulse transformer, it serves as the control signal for the switches, applied to S1, S4 and S2, S3 respectively, causing the switches on the inverter bridge arms to switch according to the resonant frequency of the load (or transducer). For loads with a fixed resonant frequency, frequency tracking technology allows the inverter to adjust its operation within a certain range around the resonant value, ensuring it operates at the resonant point. For loads with varying frequency parameters, as long as the resonant frequency of the load is within the tracking frequency range of the phase-locked loop, the phase-locked circuit can achieve automatic frequency tracking and locking. 3.2 Implementation of Phase Compensation In a bridge inverter, S1, S4 and S2, S3 commutate when the current crosses zero. However, in actual circuits, current sampling, tracking lock, and PWM signal driving all require time, which causes the drive signal to lag behind the load current by a phase angle (when the inverter operates under capacitive load). Experiments show that it takes approximately 1.5–2.5 μs from current sampling to the MOSFET fully turning on. For an inverter power supply, the phase difference between the load voltage and current caused by this time is significant, preventing the MOSFET from operating in a zero-current switching state. Furthermore, it also affects the reliable turn-on and turn-off of the switch. This paper utilizes the characteristics of the CD4046 phase-locked loop (PLL) in conjunction with a comparator to achieve phase compensation. The PLL formed by the CD4046 phase detector PD2 has the characteristic that the output signal duty cycle is always 50%, independent of the input signal duty cycle, and the rising edge of the output signal is effective. Therefore, the phase compensation circuit applies a reference bias voltage Vp to the positive terminal of the comparator input, causing the rising edge of the comparator output signal to be advanced by ΔT time. The phase compensation principle is shown in Figure 5. The control signal output by the phase-locked loop is ΔT time ahead of the current. The compensation time value can be adjusted by adjusting the bias voltage Vp. If the compensation time is greater than the circuit delay time, the load operates in an inductive state; conversely, the load operates in a capacitive state; if the compensation time is equal to the circuit delay time, the load operates in a resonant state. 3.3 Starting Circuit When the CD4046 phase-locked loop is powered on, the voltage-controlled oscillator (VCO) will operate at its lowest frequency. Applying a control voltage to pin 9 of the VCO control terminal allows the VCO output frequency to vary between the lowest and highest frequencies. Therefore, the VCO output signal can be used as an excitation signal without the need for a separate signal generation circuit. Figure 6 shows the starting circuit schematic, where pin 9 is the voltage control terminal of the voltage-controlled oscillator. When a power supply voltage (+5V) is applied to the control terminal, the VCO outputs its highest frequency. As Cr charges, the control terminal voltage gradually decreases, and the VCO slides from its highest frequency to its lowest frequency. As long as the load's natural frequency is between its highest and lowest frequencies, the VCO's output scanning frequency will cause the load to resonate, and the phase-locked loop (PLL) will enter a locked state, making startup extremely easy. After startup, diode D isolates the startup circuit from the filter circuit, and the PLL operates in a phase-difference-free automatic frequency tracking state. Experiments show that, as long as the parameters are designed reasonably, the startup reliability is >90%. 3.4 Protection and Drive Overcurrent protection measures are also designed in the control circuit of Figure 4. When the resonant current is too large, the sampling current obtained by the sampling circuit will also increase. If this current exceeds the design value, the signal sent by the sampling circuit can block the PLL after processing, preventing it from working. The subsequent drive will have no signal, and the inverter's load resonant current will decrease accordingly. When the current decreases to the normal range, the PLL will start working again. The MOSFET drive circuit in Figure 4 uses the UC3708 chip. To provide output voltage clamping protection for the UC3708, the circuit design uses the UC3611 chip, which is a quad Schottky diode array. A transformer is used for isolation between the main circuit and the control circuit. 4. Experimental Results and Conclusions The experiments show that, through APFC control, the AC input current IAC of the frequency converter exhibits a smooth sinusoidal curve, with a phase angle approximately equal to 0 with the input voltage UAC. The input power factor reaches over 0.98, which is crucial for the economical and safe operation of the power grid. By implementing zero-current resonant switching of the inverter through phase-difference-free frequency tracking control, the switching stress and electromagnetic losses of the devices are reduced, and the power factor of the frequency converter load is improved. This is of great significance for enhancing the reliability of the frequency converter and ensuring the normal and effective operation of the load. References: [1] Lin Weixun. Thyristor Intermediate Frequency Power Supply [M]. Beijing: Machinery Industry Press, 1989. [2] Huang Xiaolin, Yu Shichun. Design of Small and Medium Capacity Low Harmonic High Power Factor AC/DC (Switching Type) Power Converter [J]. Industrial Instruments and Automation Devices, 1997, (5). [3] Huang Xiaolin, Yu Shichun. Research on APFC Technology of AC/DC (Switching Type) Power Converter [J]. Electrical Drive Automation, 2000, (2). [4] Wan Xinping. Integrated Phase-Locked Loop—Principle, Characteristics and Applications [M]. Beijing: Posts & Telecom Press, 1988.