Introduction Open architecture CNC systems have become the development direction of CNC technology today, and the "PC + motion control card" structure based on the computer standard bus is the mainstream of future open CNC technology development. This type of CNC system typically uses a high-speed DSP as the CPU of the motion control card, adopts a master-slave control strategy, and utilizes the method of both the PC and the DSP reading memory to achieve communication between the upper and lower computers. It has the characteristics of strong information processing capability, high degree of openness, accurate motion trajectory control, and good versatility, and is widely used in various fields of manufacturing automation control. 1 Hardware Circuit Overall Design This project designs a multi-axis motion control card based on the PCI bus, with the TMS320F2812 DSP chip as its core. It organically combines the information processing capability and open characteristics of the PC with the motion trajectory control capability of the motion controller, using dual-port RAM as a common storage unit to achieve communication between the upper and lower computers. This provides a good development platform for realizing semi-closed-loop control of multiple motors. In this system, the PC sends various control commands, which are decoded and preprocessed by the PC program before being transmitted to the common memory—dual-port RAM—through the PCI bus interface chip. The DSP program reads instructions or data from the dual-port RAM and performs interpolation calculations based on the read instructions or data, then generates position control pulses that are input to the servo drivers of each motor axis. The servo drivers then perform interpolation based on the position commands sent by the DSP, and compare the theoretical position calculated by the interpolation calculation with the actual position fed back by the position feedback module to obtain the following error. After error compensation, the true actual position of the motor is formed, and the speed command value is calculated from the following error. Finally, PWM pulses are generated to control the motor operation. In this system, the TMS320F2812 chip acts as the main controller, coordinating the movement of each axis in the CNC system, while the servo drivers act as the actuators, controlling the actual operation of each motor. The motion control card and the servo drivers each perform their respective functions and cooperate with each other, leveraging their respective strengths. The resulting CNC system has good openness and high reliability, and can well meet the requirements of most users for multi-axis linkage CNC systems at present. The overall hardware design functional block diagram of the system is shown in Figure 1. [img=279,221]http://www.21ic.com/news/upload/2008_11/081119094324041.jpg[/img] The motion control card in this system uses the TMS320F2812 DSP chip, which has two event managers (EVA and EVB). Each event manager can generate five independent PWM signals, including three compare registers and two general-purpose timers. Theoretically, one TMS320F2812 chip can control up to 10 servo drives. Common CNC systems include three-axis linkage and five-axis linkage, and the number of motors that the motion control card can control is far greater than the number of motors in a typical CNC system. Therefore, this "PC + motion control card" CNC system not only meets the basic requirements of a multi-axis linkage CNC system but also has high scalability, even enabling joint control of multiple CNC machine tools, greatly enhancing the functionality of multi-axis linkage CNC systems. 2. Dual-Port RAM Interface Circuit Design 2.1 Connection between Dual-Port RAM, DSP, and CH365 This system uses the dual-port RAM chip IDT7025 as the buffer chip for bidirectional communication between the DSP and CH365. The IDT7025 chip is a high-speed 8K×16-bit dual-port static RAM. It provides two independent ports, allowing two (left and right) ports to read/write data simultaneously. Each port has its own independent control signal lines, address lines, and data lines, enabling high-speed data access. It can be used with most high-speed processors without inserting wait states. Dual-port RAM allows two CPUs to read any memory unit simultaneously (including reading the same address unit simultaneously), but does not allow simultaneous writing or one reading and one writing to the same address unit. The key to communication using dual-port RAM is how to handle contention and avoid read/write errors. Common methods for resolving address contention in dual-port RAM include: token passing, INT interrupt based on mailbox mechanism, and BUSY method with inserted wait cycles. This system uses the second method. The following is a brief introduction to the interrupt principle of the IDT7025: When the user needs to use the interrupt function, memory locations 1FFE and 1FFF are used as interrupt flag mailboxes to transmit command information. When the left port is defined as write mode (CEL=R/WL=VIL) and a write operation is performed in memory 1FFF, the interrupt flag INTR of the right port is low, and an interrupt request can be sent to the right port; when the right port accesses address 1FFF (CER=OER=VIL), the right port interrupt flag INTR can be cleared regardless of whether it is a read or write operation. Conversely, when the right port performs a write operation on memory 1FFE, the left port can send an interrupt request; when the left port accesses address 1FFE, the left port interrupt flag is cleared. When using interrupts, the content written to 1FFF and 1FFE is defined by the user. In this system, it is set that when requesting an interrupt, 1 or other integers greater than 0 are written to the mailbox, and when clearing an interrupt, 0 is written to the mailbox. In the system, the dual-port RAM IDT7025 serves as a shared data space between the DSP and the PC. Its right port is connected to the CH365 and mapped to its memory space; its left port is connected to the DSP and mapped to region 0 of the TMS320F2812. Since the IDT7025's power supply voltage is 5V, a voltage converter chip SN74LVTH16245 is added between the DSP chip and the dual-port RAM chip. The hardware connection diagram is shown in Figure 2. The dual-port RAM in Figure 2 is divided into two memory spaces: the PC sends instructions to the DSP by writing to the high 4KB space, and the DSP sends data back to the PC by writing to the low 4KB space. 2.2 Data Bus Expansion Circuit Design Since the system uses the dual-port RAM as a buffer chip for data transmission between the DSP and the CH365, and the TMS320F2812 has a 19-bit address bus, the IDT7025 has a 13-bit address bus, and the CH365 has a 16-bit address bus, the 13-bit address line A[O...] of the IDT7025 is extended... [12] is connected to the address lines XA[0.12] of the DSP and A[0.12] of the CH365 respectively, and the address line A0 of the CH365 is used as the enable signal for data bus expansion. Both the TMS320F2812 and IDT7025 have a data width of 16 bits. Since the I/O power supply of the TMS320F2812 is 3.3 V and that of the IDT7025 is 5 V, a voltage conversion chip SN74LVTH16245 needs to be connected between their data lines, and the direction of data transmission is controlled by the XR/W signal. The CH365 has a data width of 8 bits. To enable normal communication with the 16-bit dual-port RAM, the system uses a CPLD to expand the data bus of the CH365. The CPLD chip selected is the EPM7064 manufactured by Altera. Time-division multiplexing of the 16-bit data is performed by enabling the address line A0 of the CH365, thus solving the data bus expansion problem. Its internal logic circuit is shown in Figure 3, which mainly includes two latches (74373b) and two tri-state gate buffers (74541b). [img=406,649]http://www.21ic.com/news/upload/2008_11/081119093796133.jpg[/img] The CH365 supports PCs to read/write I/O ports or memory in units of single bytes, double bytes (words), and four bytes (double words). During multi-byte continuous read/write operations, the CH365 automatically increments the offset address by 1 after reading each byte of data to point to the offset address of the next byte. In this system, the read/write of 16-bit data is converted into time-division read/write of 8-bit data (1 byte). When the CH365 reads data from the dual-port RAM, CH365_A0 is initially low, and the lower 8 bits of data are directly read into the CH365 through tri-state gate U3, while the higher 8 bits are latched into latch U4. Then, the offset address is automatically incremented by 1, CH365_A0 becomes high, and the higher 8 bits of data are read into the CH365 from latch U4. When the CH365 writes data to the dual-port RAM, CH365_A0 is initially low, the latch U1 enable signal G is active high, and tri-state gate U2 is inactive (GN2 is high), and the lower 8 bits are written to the latch. Then, the offset address is incremented by 1, CH365_A0 becomes high, the tri-state gate U2 enable signal is active, and the higher 8 bits of data are directly written to the dual-port RAM, while the lower 8 bits are written to the dual-port RAM through latch U1 (OEN is low). The timing diagram shown in Figure 4 is obtained after simulating the above logic using "MAX+PLUS". The figures show RAM_DD and CH365_DD representing simulation results, which fully meet the design requirements. This demonstrates that by utilizing different levels of the lowest address bit CH365_A0, CH365 successfully reads/writes 16-bit data in the dual-port RAM through two consecutive read or write operations. Furthermore, the data read/write timing perfectly matches the CH365's read/write timing, facilitating software programming. [img=302,181]http://www.21ic.com/news/upload/2008_11/081119093796134.jpg[/img] 3. Upper/Lower Computer Communication Software Design After the hardware circuit is implemented, the completed board is inserted into the PCI slot of the PC. After powering on, the CH365 driver is installed according to the system prompts. After correctly installing the hardware, the communication software between the PCI and DSP can be written and debugged in the VC environment using API functions. As mentioned above, the upper 4 KB of the dual-port RAM is used for the PC to download data to the DSP. If the data is larger than 4 KB, there is a problem that not all the data can be downloaded to the DSP at once. Therefore, a method of writing data to the dual-port RAM in a loop is adopted. That is, the PC writes 4 KB of data to the dual-port RAM at a time, and then requests an interrupt from the DSP. The DSP responds to the interrupt and copies the 4 KB of data to other large-capacity storage space (such as extended SRAM) of the DSP, and then releases the dual-port RAM space. At this time, the PC can write another 4 KB of data, and so on, until all the data is written to the DSP. Part of the code is as follows: [img=407,865]http://www.21ic.com/news/upload/2008_11/081119094324042.jpg[/img] The data feedback function is mainly implemented by the CH365 responding to the DSP interrupt. After the DSP program writes data to the lower 4 KB of the dual-port RAM, it requests an interrupt from the CH365. The CH365 responds to the interrupt, feeding the data back to the PC and displaying it on the HMI. The interrupt function code is as follows: [img=383,595]http://www.21ic.com/news/upload/2008_11/081119093796136.jpg[/img] Conclusion With the development of computer and electronic technologies, the application of high-speed, powerful digital signal processors to motion control can realize complex control algorithms and achieve high precision, high speed, and multi-axis linkage, playing an increasingly important role in CNC applications. Fast and accurate communication is the foundation of such motion controllers. The communication method introduced in this article has the advantages of reliable performance, simple hardware structure, and low cost, and has good application prospects.