Introduction
The CAN bus, with its low development and maintenance costs, high bus utilization, long transmission distance (up to 10 km), and high transmission rate (up to 1 Mbps), enables users to build stable and efficient fieldbus networks. The CAN bus has been widely used in various automation control systems, such as automotive electronics, automatic control, intelligent buildings, power systems, and security monitoring. As the CAN bus network area expands, direct data transmission between two nodes will be insufficient for long-distance communication requirements. CAN repeaters serve as relay stations to extend the CAN bus communication distance, and their communication efficiency and reliability directly affect the CAN bus's communication capabilities. Traditional single-MCU-based CAN repeaters struggle to meet the requirements for relaying large amounts of data. This paper presents a high-performance CAN bus repeater based on a dual-MCU design.
1 System Overall Design
The CY7C136 is a 2 KB high-speed CMOS static RAM. It has two sets of data lines and two sets of address lines on the same RAM chip. Control of each port is independent, allowing data to be accessed at any location in the memory.
The dual-port RAM serves as a shared resource for the two MCUs, with one port connected to MCU1 and the other to MCU2. Data received from the SJAl000 CAN bus interface 1 is fed into the dual-port RAM, then retrieved by MCU2 and sent to the SJAl000 CAN bus interface 2; conversely, data received from the SJAl000 CAN bus interface 2 is also fed into the dual-port RAM and retrieved by MCU1 before being sent to the SJAl000 CAN bus interface 1. Since the MCU's address and data buses are multiplexed, a latch is used for address latching. The overall hardware structure is shown in Figure 1.
2 Hardware Circuit Implementation
The circuit uses two AT89C52 8051 series microcontrollers, which are low-cost, have a short development cycle, are easy to implement, and are highly reliable. MCU1 and MCU2 communicate and respond through P1.5, P1.6, and P1.7 of port P1 to ensure the security of system memory access.
2.1 MCU Main Control Circuit
The peripheral devices connected to MCU1 (AT89C52 chip 1) include a dual-port RAM and a CAN bus controller. To prevent address conflicts, a 74LS138 decoder is used for address decoding. The AT89C52's P0 port is an address/data multiplexed port, and a 74HC573 is used as the address latch. Since the circuit principles of MCU1 and MCU2 are the same, this article only describes the control circuit of MCU1. The circuit principle of MCU1 is shown in Figure 2.
2.2 Dual-port RAM interface circuit
The dual-port RAM circuit interface is shown in Figure 3. The dual-port RAM chip CY7C136 acts as a data relay station for the two MCUs, connecting to the corresponding pins of the two MCUs respectively. Specifically, pins I/O0L to I/O7L of the CY7C136 are connected to pin PO of the first AT89C52 (MCU1), and pins I/OOR to I/O7R are connected to the second AT89C52 (MCU2). YOAOUT is the chip select signal for MCU1 to read and write to the dual-port RAM, and Y1AOUT is the chip select signal for MCU2 to read and write to the dual-port RAM. The MCU's read/write control signal lines are also connected to the corresponding read/write control signal lines of the dual-port RAM.
2.3 CAN Bus Controller Interface Circuit
The CAN bus controller uses the SJAl000. The YO pin output of the 74LS138 decoder is used as the chip select signal for the SJAl000. The interrupt pin is connected to the INT0 pin of MCU1 as the trigger signal for handling CAN receive interrupts. The circuit principle is shown in Figure 4.
3. Software Design and Implementation
3.1 Storage Space Allocation Concepts
To achieve the highest efficiency in the dual-port RAM, the 2 KB storage space is designed as two 1 KB circular queues. The structure of each circular queue is shown in Figure 5 (the shaded area in the figure is the area where data is stored, and the unshaded area is the free area).
3.2 Program Control Flow
The repeater merely relays data from the bus, and since this data is random, reception is done via interrupts. At any given moment, as long as the SJAl000 successfully receives a data frame, it requests an interrupt from the MCU responsible for that port to receive the data and send it to the circular queue.
When there is data to be sent in the circular queue, the program's processing flow is shown in Figure 6 (where tail and head are the tail and head pointers of the circular queue, respectively). The MCU first obtains information from the other party's circular queue, primarily checking if the queue is empty. If empty, no operation is performed. If not empty, there is data to be sent, and a data transmission is initiated. If the transmission is successful, a handshake signal is used to notify the other party to modify the circular queue pointer.
4. Testing
A stress test (high data load rate test) was conducted on a dual-MCU repeater based on dual-port RAM. 10,000 frames of data were loaded onto two CAN ports over a short distance to test the repeater's successful relay performance. The results are shown in Table 1 (the table data represents the number of successfully relayed frames). According to CAN bus specifications, its average load rate should not exceed 65%, and traditional single-MCU CAN repeaters rarely achieve an average load rate of 60%. Table 1 shows that the performance of the CAN repeater is significantly improved after introducing dual MCUs, enabling stable operation even under load rates exceeding 60%. The issue of circular queue overflow can be resolved by increasing the size of the dual-port RAM.
ConclusionThe design of a CAN bus repeater using dual MCUs and dual-port RAM solves the problem that a single MCU cannot quickly handle the heavy load of the CAN bus, greatly improving its performance and efficiency. This provides a good technical platform and solution for the optimized design of CAN repeaters in the engineering field.
