Wireless video surveillance systems are crucial equipment in sectors such as public security, transportation, and water conservancy. Currently, wireless video transmission equipment primarily uses microwave technology, which has a fatal weakness: short transmission distance. The transmission distance is significantly reduced by obstacles, a problem that has remained largely unresolved for many years. With the rollout of GPRS and CDMA1x public wireless data networks by operators in most parts of China, video transmission via these networks has become a hot research and application area, as it can completely solve the short-range problem of microwave transmission. However, due to the narrow and unstable bandwidth of public wireless data networks, video compression algorithms with low coding efficiency (such as H.263 and MPEG-4) result in unsatisfactory transmission quality, failing to meet the requirements of most monitoring scenarios. H.264, the latest video compression standard developed by JVT, offers 50% lower bitrate than H.263 and MPEG-4 at the same quality and supports wireless network transmission. However, its computational complexity is 3-5 times that of H.263 and MPEG-4, making it unsuitable for most CPU systems. The TMS320DM642 is TI's latest high-performance digital media processor, with an instruction set of up to 4800 MIPS, which can meet the requirements of real-time H.264 encoding algorithms. This paper designs an embedded system based on the TMS320DM642, adopts the H.264 video encoding algorithm, and successfully develops a wireless video surveillance system based on CDMA transmission. 1 Wireless Video Surveillance System Composition 1.1 Wireless Video Surveillance System Design Requirements This system requires an embedded video transmitting terminal to compress the acquired video images in real time and transmit them through a CDMA network. The receiving end uses a PC to decode and display the received video data. The embedded video transmitting terminal has the following requirements: ① One PAL/NTSC standard analog video input and one analog audio input; ② CDMA access method to transmit video data through the network; ③ Local storage of video using a CF card or hard disk; ④ Adjustable parameters such as the size and frame rate of the transmitted and saved images; ⑤ Remote control via wireless network and low power consumption. 1.2 Overall System Design Due to the narrow bandwidth and large bandwidth fluctuation of the CDMA wireless network, H.264 is used as the video compression algorithm in the system. Meanwhile, local storage and CDMA-transmitted video differ in image size and frame rate, requiring separate encoding structures. Figure 1 shows the overall system structure block diagram. The system mainly includes a DM642 CPU, video input, audio input/output, hard disk interface, serial port, and USB communication (USB 2.0) modules. It also includes a real-time clock (RTC), display and I/O interface (LCD & I/O), SDRAM, FLASH, and power supply modules. The following will analyze and design each functional module in detail. Figure 1: Video Transmission Terminal System Block Diagram 2. Wireless Video Surveillance System Hardware Design 2.1 Introduction to TMS320DM642 The TMS320DM642 is a high-performance digital media processor launched by TI for multimedia processing applications. This processor is specifically tailored for the video and imaging market, particularly suitable for VoIP video, video-on-demand (VOD), multi-channel digital video recording applications, and high-quality video encoding and decoding solutions. The DM642 processor integrates a TMS320C64X DSP core, achieving an instruction set of 4800 MIPS at 600MHz. Its powerful processing capabilities enable real-time H.264 encoding and decoding. The DM642 also integrates an External Memory Interface (EMIF) control unit, allowing direct connection to external SDRAM and FLASH memory via 20 address lines and a 64-bit data bus. In this system, 100MHz SDRAM is used; for signal integrity, the SDRAM is directly connected to the DM642, while the FLASH memory is connected via a bus driver. The DM642 has three video input ports, supporting various resolutions and standards such as CCIR601, ITU-BT.656, and BT.1120. Each port is 20-bit wide and can be flexibly configured as one 20/16-bit or two 10/8-bit channels. Each port can be configured as either video input or output. In this system, VP0 is connected to the SAA7113H for video input acquisition. The SAA7113H is a 9-bit video decoder. Internally, it consists of a two-channel analog preprocessing circuit (video source selection, anti-aliasing filter, and ADC), gain control, a clock generation circuit (CGC), a multi-standard digital decoder, and brightness/saturation control circuits. It supports multiple video input formats such as PAL and NATSC, and outputs in the standard ITU.656 YUV 4:2:28-bit format. It is controlled via an I2C bus, requires only a 24.576MHz external crystal oscillator, operates on a 3.3V power supply, and consumes less than 0.5W. The interface between the SAA7113H and DM642 is shown in Figure 2. Figure 2: SAA7113H and DM642 Interface. 2.3 Audio Input/Output (CODEC) Module The DM642 has a multi-channel audio serial port (McASP) and two multi-channel buffered serial ports (McBSPs), but these are multiplexed with the video ports. In this system, McBSPs1 in VP1 is used as the interface for connecting to the audio codec. The TLV320AIC23B is a high-performance stereo audio codec chip from TI. It features a built-in headphone output amplifier, supports both MIC and LINEIN input methods (selectable), and offers programmable gain adjustment for both input and output. The AIC23B's analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) are highly integrated within the chip, employing advanced Sigma-delta oversampling technology. It can provide 16-bit, 20-bit, 24-bit, and 32-bit sampling within a frequency range of 8kHz to 96kHz, with output signal-to-noise ratios of 90dB and 100dB for the ADC and DAC, respectively. The AIC23B also boasts very low power consumption, consuming only 23mW in playback mode. The interface between the AIC23B and DM642 is shown in Figure 3. Figure 3: AIC23B and DM642 Interface. 2.4 CDMA Wireless Transmission Serial Port Module This system uses the Q2358C serial interface module as the CDMA access device, supporting voice communication, Chinese and English SMS, and Dual-Tone Multi-Frequency (DTMF) functionality. The DM642 has a baud rate ranging from 300 to 115, 200 bit/s, supports a maximum internet speed of 153 kb/s, and communicates via an RS-232 serial port using the AT command set. The DM642 lacks an asynchronous universal serial interface and requires an extended asynchronous communication chip for serial communication. The TL16C752B is a UART transceiver with a maximum baud rate of 3 Mb/s (using a 48 MHz clock source). It has an internal 64-byte transmit/receive FIFO, and the start and stop of the receive FIFO can be programmed in software. It supports multiple baud rates and multiple serial data formats. The DM642 is connected to the EMIF via address lines A0-A2, data lines D0-D7, and read/write control signals IOR/IOW, all connected to the driven bus. The strobe signals CSA/CSB are generated by GAL. The TL16C752B and the Q2358C module are connected via a MAX3243 for level conversion. Figure 4 shows the connection method for one serial interface. 2.5 DE and USB Communication Module This system requires local data storage for the captured video, using CF cards or IDE hard drives for data saving. Data stored on the CF card or DE hard drive is retrieved when needed via USB 2.0. The DM642 interface with the DE is controlled by signals generated by the GAL16LV8. The TUSB6250 uses a USB 2.0 to ATA/ATAPI bridge with an embedded 8051 core, fully compatible with the USB 2.0 standard, supporting eight configurable terminals (four inputs and four outputs). It integrates the USB storage device transmission protocol internally, seamlessly connecting with ATA/ATAPI devices. The internally integrated 60MHz 8051 microprocessor has an instruction speed of up to 30MIPS, 40kbyte RAM that can be flexibly configured as data or code RAM, 13 general-purpose I/O ports for various communication and control uses, and an I2C interface. In this system, communication between the DSP and the TUSB6250 is achieved through the I2C and HPI buses. See Figure 5 for the DE and USB interfaces. 2.6 Power Supply and Other Modules The DM642 uses a dual power supply: a 1.4V core power supply consuming 890mA, and a 3.3V I/O power supply consuming 210mA. Because the core power supply voltage is low and its current consumption is high, using an LDO power supply would be inefficient and increase power consumption. Therefore, this system uses two switching power supply chips, TPS54310, to generate 3.3V and 1.4V power supplies respectively, achieving a power efficiency of over 90%. The DM642 provides 16 general-purpose I/O ports for keyboard input, control switch inputs and outputs. The DM642's video port VP3 is configured for direct connection to the LCD. Additionally, the system uses a DS1338 as a real-time clock to provide real-time time information. 3. System Design Considerations 3.1 Schematic Design The internal operating frequency of the DM642 is obtained by multiplying the external clock input by the internal PLL. The PLL multiplication can be selected as x1, x6, or x12 through the CLKMODE1 and CLKMODE2 pins. Therefore, these two pins must be connected to corresponding adjustable resistors so that the DM642 can operate at different speeds. The DM642 has multiple BOOT startup modes to choose from. If the EMIFA FLASH is selected as the startup, the FLASH chip select must be connected to TCE1. The DM642 can select the big/small byte order mode, and the peripheral PCI, HPI, and EMAC modes. The selection is determined by the level of the LENDIAN, PCI_EN, PCI_EEAI, HD5, and MAC_EN pins during reset. It is necessary to consider making the level values ​​adjustable during reset. For the emulator's EMU[1:0], ensure that it is pulled up and TRST is pulled down. In addition, the AARDY pin should be kept high when not in use, and the NMI pin should be grounded when not in use. When selecting HPI mode, the HPI control signal level should be correct, and other unused input pins should be handled correctly. 3.2 PCB Design The DM642, as a high-performance digital media processor, not only has high internal operating frequencies of 600MHz, 720MHz, and 1GHz, but also a bus speed of 100MHz or 133MHz with external SDRAM. If the external SDRAM cannot reach the desired speed due to wiring reasons, it will reduce the system performance. For signal buses above 100MHz, there are signal integrity issues. To ensure signal integrity, the following methods should be adopted: the clock line of SDRAM should be as short as possible, and the lengths to the two SDRAMs should be as equal as possible; other peripherals such as FLASH should not be directly connected to the data and address buses, but should be connected through buffer chips (such as SN74LVT16245B); small-value resistors should be connected in series on the high-speed bus, and the resistance value can be obtained through simulation. At the same time, impedance limiting is required for the circuit. The DM642 has an internal PLL. External devices connected to the PLL should be placed as close to the chip as possible and must be on one side of the circuit board. JTAG cable length should not exceed 6 inches; if it exceeds 6 inches, a driver is required. This system contains both analog and digital components; careful design of the analog and digital power supplies is crucial to minimize interference from digital signals to analog signals. Otherwise, the acquired video signal will exhibit snow-like patterns and stripes, and the audio signal will produce noise. Dedicated power supplies should be used for the video and audio chips whenever possible, and analog and digital grounds should be single-point connected or connected using ferrite beads. 4. Conclusion Based on the above hardware design, an embedded wireless video surveillance system based on the DM642 has been completed. This system uses a high-speed DSP as its core, supplemented by corresponding peripheral circuits, to achieve real-time H.264 video encoding and decoding. Currently, the system has successfully passed debugging and is running stably continuously, providing a practical solution for wireless video surveillance in industries such as public security, transportation, and water conservancy, and has very high application value. Editor: He Shiping