Introduction With the large-scale deployment of new-generation combat aircraft, the maintenance tasks of airborne radar equipment are becoming increasingly heavy, making modern simulation testing systems crucial maintenance equipment. Radar signal simulation is indispensable in testing systems. However, using function/arbitrary wave generators to construct testing systems not only increases system costs but also adds unnecessary burdens to system software design. Therefore, a CPLD-based radar simulation signal implementation scheme is proposed, which can provide airborne radar testing systems with various typical repetition rate pulses and guidance signals. Structure of the Radar Simulation Signal Generator The radar simulation signal generator mainly consists of two parts: input/output control and a CPLD chip that generates the simulation signal. The input/output control signals are generated by the industrial control computer of the testing system through a digital I/O card. When the industrial control computer outputs a valid signal through the digital I/O card, the generator will output a corresponding pulse signal. The structure of the radar simulation signal generator is shown in Figure 1. Figure 1: Structure of the Radar Simulation Signal Generator. In the diagram, the control signals of the radar simulation signal generator include a radar simulation signal pulse switch, a UNITED switch, a guidance signal SA-H switch, a guidance signal SA-L switch, and an illumination output SA-W switch. All the above switches are active low. When the "pulse switch" is active, the radar simulation signal generator is in operation. At this time, any active control signal will cause it to output the corresponding radar simulation signal. When "SA-H" is active, "out1" outputs a high repetition rate (PRR) pulse signal; when "SA-L" is active, "out1" outputs a medium repetition rate (MRR) pulse signal; when "SA-W" is active, "out2" outputs an illumination pulse signal; when "UNITED" is active, "out3" outputs a combined pulse signal, which adds a high or medium RPR pulse signal to the low level of the illumination pulse. CPLD Internal Circuit Design and Simulation: The CPLD used in this design is the Altera EPM7128SLC84, belonging to the MAX7000 series. The MAX7000 series provides 600–5000 usable gates (1200–10000 gates on the device), a pin-to-pin delay of 6ns, and a counter frequency of up to 151.5MHz. The CPLD is the core of the radar simulation signal generator. Its internal circuitry is mainly divided into six sub-modules: a 5-division and pulse width shaping module, a 10-division and pulse width shaping module, a 60-division and pulse width shaping module, a 100-division circuit, a 625-division circuit, and a pulse output selector. The connection relationship between these modules is shown in Figure 2. The clock pulse input CLK frequency is a 10MHz signal provided by an external crystal oscillator, providing a 50ns pulse width input signal for the 10-division and pulse width shaping circuit, the 60-division and pulse width shaping circuit, and the 100-division circuit. The 100-fold and 625-fold frequency divider circuits are designed using the built-in macro function LPM-COUNTER (a presettable counter) of MAX+PLUSⅡ. A 10MHz signal is input through the clk terminal of LPM-COUNTER, while cout serves as the output of the divided pulse. The modulus and width parameters are set according to the required pulse frequency. Taking the 100-fold frequency divider circuit as an example, setting the modulus to 100 and the corresponding width to 7, after all control signals of the macro function are set to counting mode, counting begins when the rising edge of clk arrives. When the count reaches 100, the counter resets to zero and outputs a pulse with a pulse width equal to the clk clock cycle at cout. This process repeats, achieving the 100-fold frequency division. Figure 3 shows the simulation waveform of the 100-fold frequency divider. The 60-fold frequency divider and pulse width shaping circuit generates a high repetition rate pulse with a period of 6μs and a pulse width of 1.2μs, as shown in Figure 4. The frequency divider circuit uses the same design method as described above. Simply set the modulus and width parameters to 60 and 6 respectively to generate a pulse with a period of 6μs and a pulse width of 100ns (clk100ns in Figure 5). This signal is used as the clock signal for the D flip-flop, whose input is always kept high. Thus, the output of the D flip-flop will always remain "1" after the rising edge of the clock. However, to obtain a 1.2μs pulse, the D flip-flop must be cleared after 1.2μs. The clear signal is designed using the LPM-COUNTER function. The function's input signal is a 10MHz pulse signal, with the modulus and width parameters set to 13 and 4 respectively. When the count reaches 13 (the 13th rising edge appears at the clk input, i.e., 12 clock cycles, 1.2μs), the counter resets to zero and generates a pulse at cout. This pulse is then connected to the D flip-flop (D:CLRN in Figure 5) via an inverter to clear its output to "0". To prevent the counter from being in counting mode when the D flip-flop outputs "0", the output of the D flip-flop is connected to the synchronous clear terminal aclr of the LPM-COUNTER via an inverter. This allows the desired high repetition rate (f166k in Figure 5) to be obtained at the output of the D flip-flop, and Figure 5 shows its simulation waveform. [align=center] [/align] Figure 5 Simulation waveform of high repetition rate signal. The 10-division and pulse width shaping circuit generates a medium repetition rate pulse with a period of 60μs and a pulse width of 3μs. Its design uses the same method as the high repetition rate signal, except that the high repetition rate signal is used as the input of its 10-division circuit. The 5-division and pulse width shaping circuit generates an illumination pulse with a period of 50ms and a pulse width of 31.25ms. It mainly consists of an LPM-COUNTER function and a decoder 74138. The clock input of the LPM-COUNTER uses a pulse with a period of 6.25ms and a pulse width of 10us generated by 100-division and 625-division (see Figure 2). Setting the width parameter of the LPM-COUNTER function to 3, its q[2..0] outputs 0 to 7, which are used as inputs to the decoder. At this time, the eight outputs y0 to y7 of the decoder will each hold a "0" for 6.25ms. Using y0 to y4 as inputs, a pulse width of 31.25ms can be obtained by inputting to the AND gate at input 5. The eight clock cycles of the decoder constitute a 50ms pulse period. Figure 6 shows the simulated waveform of the illumination pulse. Figure 7 shows the simulated waveform of the combined state. The output selector mainly completes the selection of the combined state and each pulse output pin. The combined state output uses the illumination pulse to control the aclr clear signal of the LPM-COUNTER function for high and medium repetition frequency signals, so as to achieve the output of the control repetition frequency signal. Figure 7 shows the simulated waveform of the combined state. Edited by: He Shiping