Introduction With the development of integrated circuits, using large-scale integrated circuits to design various high-speed, high-precision electronic instruments has become an effective method. Electronic instruments made using this technology have simple circuit structures, reliable performance, accurate measurements, and are easy to debug. This paper uses the Altera Cyclone II series FPGA device EP2C5 to design a high-precision phase measuring instrument. The signal source required for measuring the phase difference is generated internally within the FPGA using the DDS principle. Then, the distance between the zero-crossing points of two sine waves is calculated using a high-speed clock pulse. Finally, the final phase value is obtained through a certain operational circuit, with a phase measurement accuracy of 1°. [align=center]Figure 1 Hardware structure diagram of the phase measuring instrument[/align][align=center]Figure 2 Block diagram of the DDS-based digital phase-shifting signal generation module[/align]　　[align=left] System Hardware Design This FPGA-based phase measuring instrument consists of an FPGA, a high-speed DAC, and a voltage comparator. Its system hardware structure is shown in Figure 1. The measuring instrument uses buttons to preset the frequency and phase of a sine wave. The control module inside the FPGA calculates and generates the frequency and phase control words required for the sine wave, then inputs the control words into the DDS module to generate waveform data output. This data is then output as two sine waves via a 10-bit high-speed DAC THS5651. When measuring the phase difference, the phase-shifted sine wave output in Figure 1 is split into two paths. One path is directly shaped by the voltage comparator LM311 and input to the phase measuring module; the other path first passes through the circuit under test, then is shaped by the voltage comparator before being input to the phase measuring module, thus obtaining the phase shift of the sine wave after passing through the circuit under test.[/align] Figure 3: Top-level block diagram of the control module　　[align=left][b]FPGA-based Hardware Circuit Design[/b] DDS Phase-Shift Signal Source Design The basic principle of DDS is to generate waveforms using the sampling theorem and a lookup table method. The phase-shift signal generation module of this system is shown in Figure 2. In Figure 2, the adder and register are cascaded to form a phase accumulator. The phase accumulator is triggered by a clock pulse, thereby continuously accumulating the frequency control word. Each overflow of the phase accumulator completes one periodic operation, and this period is one frequency period of the DDS synthesized signal. [/align][align=center]Figure 4 Block Diagram of Phase Measurement Module[/align] The data output by the phase accumulator is used as the phase sampling address of the waveform memory. The waveform sample value stored in the waveform memory is looked up through the lookup table, thereby completing the phase-to-amplitude conversion. Then, the output of the waveform memory is sent to the DAC, which converts the digital waveform amplitude into an analog waveform of the synthesized frequency. In Figure 2, FWORD is a 10-bit frequency control word; PWORD is a 10-bit phase shift control word used to control the phase shift of the sinusoidal signal output; SINROM is used to store the sinusoidal wave data, with 10 data lines and 10 address lines. The data file is a MIF file (data depth 1024, data type decimal), which can be generated by Matlab. The data storage unit is generated using a custom ROM method. OUT and FOUT are both 10-bit outputs, connected to two high-speed DACs THS5651 respectively.　　**[b]Control Module Generation[/b]** During waveform generation, the frequency and phase control words required by the DDS module are provided by the control module written inside the FPGA. The top-level block diagram of the control module is shown in Figure 3. In Figure 3, B1, C10, D100, and P1K are the frequency step input terminals; Re is the reset terminal; PW1 and PW10 are the 1/10/2000 and 1/20000 respectively. `cout` is the frequency control word calculation module, which completes the conversion from the frequency step value to the binary frequency control word. `cout360` is the phase input calculation module, which calculates the actual phase shift value (0°359) from the pulse input at the phase input terminal. `add_data_rom` is the ROM that stores the phase control word. Its data file is a MIF file, and its 360 address values ​​correspond to 0°359 and 1/2000 respectively. The data in each address is the address value of the sine wave ROM corresponding to each phase value. Since the sine wave ROM divides a waveform into 1024 points, then 0.359 is stored in 360 points of the INROM. Considering that 1024/360 = 2.84 is not an integer, in order to reduce phase shift error and improve phase shift accuracy, this design adopts a segmented processing method, dividing the 360 ​​addresses into 60 groups. The distance between points in the 6 addresses of groups 15, 30, 45, and 60 is 3; the distance between the first 5 points in the remaining groups is 3, and the distance between the 5th and 6th points is 2.　　**[b]Phase Measurement Module Design Principle[/b]** The phase measurement of this system uses a high-speed clock pulse to measure the distance between the zero-crossing points of two waveforms. The block diagram of the phase measurement module is shown in Figure 4. In Figure 4, A and B are two square wave inputs, CLK is a 50MHz clock input, and the dfd2 block is a falling-edge triggered frequency divider module. The purpose of dividing A and B by 2 is to make the phase measurement range from 0° to 180° to 0° to 360°. OR is an XOR gate, and its output signal pulse width is (ba). clxw is a high-speed counter that calculates the length of (ba) using a 25MHz high-frequency clock. The fb360 module is a multiplier module, mainly performing the operation of (ba) × 360. The bpsc module is a frequency divider module that divides the 25MHz clock signal by (ba) × 360, making its output signal pulse width Tclk × (ba) × 360 (Tclk is the 25MHz clock period). xwc is a phase difference counting module. It takes an input pulse from phase A, calculates the length of Tclk × (ba) × 360, then performs the calculation of (ba) × 360/a, and outputs the phase difference value. Simultaneously, this module also sends the measured phase difference value to a digital tube display. In the simulation of this module, the frequency was manually set to 10kHz and the phase difference to 72.　　　**System Verification and Debugging** During the system verification, the frequency and phase values ​​of the waveform were set via external buttons through the control module. A 10-bit DAC THS5651 was connected to the output terminals FOUT and POUT of the DDS module to generate the waveform. Observation of the two waveforms on an oscilloscope revealed that the waveforms were relatively stable, and the frequency matched the set value. Furthermore, to measure the accuracy of the phase shift generated by the DDS module, a phase shift value was manually set through the phase input terminal. The waveforms output from the reference waveform terminal and the phase shift output terminal were shaped, and the phase difference between the two waveforms was measured using a phase measurement module. Hardware debugging showed that the measured phase difference was completely consistent with the set phase difference, thus proving that the system is accurate and stable.　　　Conclusion This system uses Altera's Quartus II 4.1 as the hardware development platform and employs VHDL for circuit design. The design is functionally divided into modules, facilitating debugging, modification, and upgrades. Furthermore, the system design extensively utilizes synchronous timing circuits to implement the functions of each process module, effectively avoiding circuit glitches. In addition, the phase difference counter in the phase measurement module incorporates a latching function, which contributes to the stability of the output phase difference value display.