Abstract: To address the challenges of heavy data processing tasks and diverse business types in large-scale systems, this paper presents a distributed system design based on Compact PCI (CPCI), which enables collaborative work among system boards and cross-bus remote memory access. This paper proposes a message storage mechanism and address information maintenance strategy based on a "drawer mechanism," achieving accurate and efficient distributed cross-bus communication. Keywords: Compact PCI; Distributed system; Drawer mechanism Abstract: To solve the problems of mass data processing and support various services in large-scale systems, this paper presents a design of a distributed system based on Compact PCI (CPCI), which implements distant memory access and cooperation between boards through the CPCI bus. This paper proposes a packet storage mechanism and address information maintenance strategy based on a "drawer mechanism." The design implements correct and efficient distributed data communication through the CPCI bus. Keywords: Compact PCI; Distributed system; Drawer mechanism 1. Introduction With the rapid development of network and communication technologies, the tasks of data processing and communication in network environments are constantly increasing. In more and more fields, large-scale systems are needed to undertake heavy data tasks and support various types of task processing. To process large amounts of data in real time, large-scale systems need to distribute data across multiple modules for parallel processing. Simultaneously, for various heterogeneous network data, different functional modules process different types of data separately, and then real-time communication is performed based on a unified platform. To meet such requirements, large-scale systems should adopt a distributed network architecture, and should also have openness and good scalability to adapt to the ever-changing application environment and needs; each module in the system should be responsible for processing different types of data, and should have relative independence and autonomy, while being interconnected at different levels to achieve mutual access and collaborative work; the system should also have good integration, requiring an effective component construction framework at the functional level, and a unified data interaction platform at the component level [1]. Based on the above analysis, we selected CPCI bus as the data communication platform for the distributed system. CPCI bus technology is a combination of PCI bus technology and mature European card assembly technology. In terms of electrical, logical and software functions, it is fully compatible with the PCI standard, and breaks through the limitation of 4 slots in the PCI standard. Compared with VME bus modules, it has a lower price, and has advantages such as openness, easy expansion and high density, while achieving a high availability of 99.999%. Using CPCI bus technology and hardware interface design specifications, it can leverage its multi-module plug-in card design advantages to support distributed processing of multiple services and achieve seamless connection of modular data processing units, providing high-speed and reliable guarantees for distributed data exchange. It is very suitable as a communication platform for distributed system business processing and is also suitable for widespread application in communication and embedded systems [2-4]. This paper presents a communication system design based on CPCI bus. The system adopts a distributed network architecture and supports the processing and data interaction of multiple packet switching services. The paper first presents the system structure and principle design, and then proposes a message storage and address information maintenance strategy based on the "drawer mechanism" to address the difficulties of cross-bus communication of distributed business processing modules. It describes the implementation of key technologies such as interference-free data transmission and finally gives a technical summary and outlook. 2. System Overall Design 2.1 System Structure Characteristics The distributed system structure we designed is shown in Figure 1. Different device cards in the system independently process the corresponding business data, convert it into unified IP data for interoperability, and maintain their own routing tables to independently complete data forwarding. The system distributes interfaces with specific business networks across various device boards for standard access channel adaptation, and distributes various network data across boards for processing and forwarding, achieving a perfect combination of centralized configuration, distributed access, and data processing. In the CPCI distributed bus architecture, the backplane provides physical connections and circuit guarantees for bus switching, and the system slots on the backplane provide functions such as bus arbitration, clock distribution, and restarting of each board on the backplane; simple interface boards, intelligent slave devices, or bus control devices can be placed on the peripheral slots [2,3]. Each CPCI board has a processor and an embedded real-time system. The processor uses Motorola's PowerPC-860, and PLX's 9054 and 9056 PCI bridge chips are used to build an efficient and stable transmission bridge between the PowerPC-860 and the CPCI bus. The PLX 9054/9056 chip implements the functions of CPCI master control device, supports PCI2.2 protocol, simplifies the design of connecting to PowerPC, has good compatibility, and can be easily expanded to 66MHz clock and 64bit PCI bus. In particular, the PLX 9056 has an embedded bus arbiter, which can reduce the system size and make the system more stable[5]. [align=center] Figure 1 Data communication system structure diagram[/align] 2.2 System resource sharing and information exchange The system adopts a distributed architecture based on CPCI single bus multiprocessor/multioperating system. Each board in the system has an independent CPU and operating system, address and memory space, as well as independent I/O and interrupt. It can independently complete data operations. Each board can be regarded as a computer host. The topology formed by the distributed system is a fully connected network. Each node in the network can directly access other nodes. From the perspective of CPCI bus transmission, all boards on the slots are equal and can act as masters to actively initiate bus transmission. For this bus-based distributed architecture, we designed a cross-bus memory access mechanism. This mechanism maps the system memory or device memory (such as memory expansion cards) of other boards in the system to the local address space, and then accesses the mapped memory in the same way as system memory. This allows each board to access the memory resources of other boards on the bus. 2.3 Unified and Standardized Access Interface: Heterogeneous networks are adapted to the distributed system through standard channels. Non-IP data such as voice, X.25, and serial data are converted into IP data by a data adaptation module. The embedded real-time systems of each board in the system process and interact with the data. Various heterogeneous networks are connected to corresponding network devices in the embedded system. The network device driver calls the unified interface provided by the CPCI bus driver to realize data transmission between the real-time system and the bus. When sending data, the network device driver controls the bridge chip through the bus driver to perform address translation, data forwarding, interrupt generation, etc., generating corresponding bus operations to send data to the bus. When receiving data, the bus driver responds to interrupts, receives data from the corresponding address segment on the bus, and performs data parsing, address translation, data forwarding, and other interrupt generation operations in the interrupt service routine. We use the Linux operating system, whose network system is mainly based on the UNIX socket mechanism. Data is transferred between the system protocol stack and the driver through a dedicated data structure (sk_buff). The data transmission process between the real-time system kernel and the CPCI bus is shown in Figure 2: [align=center] Figure 2 Data Transmission Flowchart[/align] 3. Key Technologies 3.1 "Drawer Mechanism" for Message Storage All boards in the system share a single CPCI bus. We propose a message storage strategy based on the "drawer mechanism" to ensure interference-free data transmission between boards. During the initialization phase of a board joining the system, the system board allocates an independent PCI bus address range for each board on the bus. When other boards send data to it, the data is written to the designated address range. A board will receive data from different boards. To avoid interference caused by boards sending data to the same base address, the same address range is allocated with independent read/write spaces of the same size for other boards, which we call "drawers." Data from a particular board is sent to its corresponding "drawer," with data stored sequentially rather than overwritten, to ensure efficient board data processing. When the data length exceeds the remaining space in the drawer, it is stored from the beginning of the circular buffer. The "drawer mechanism" is shown in Figure 3. The left squares represent different boards on the bus, and the right side represents the PCI bus address space. The address range corresponding to board B is from point a to point e. The space between points a and b is only used for data transmission from board A to B, the space between points b and c is only used for data transmission from board C to B, and so on. [align=center]Figure 3 Board Data Reception "Drawer"[/align] Based on this message storage mechanism, we define several address tables to maintain data transmission related address information. The system board maintains a static base address table, recording the pre-allocated base address for each board in each slot. All boards maintain a board address mapping table and a transmission address offset table. The board address mapping table is a structure array, where each item represents a card slot. It contains address information such as board name, slot number, base address, and address range for configuration during data transmission. Its data structure is as follows: `typedef struct _BUS_ADDR_MAPPING_INFO{ char board_name[BOARD_NAME_LENGTH]; int slot_number; unsigned long base_addr; unsigned long range; }BUS_AddrMapping_Info， *P_BUS_AddrMapping_Info;` The transmission address offset table is an unsigned integer array used to record the address offset of each board during inter-board data transmission. The initial value is zero. After each transmission, the address offset of the receiving board is increased by the length of the data transmission. When the address space is insufficient to store the data to be transmitted, the offset address is set to zero, and the data is rewritten from the beginning of the region. Its data structure is defined as follows: `u32 current_offset_table[NUM_OF_SLOT] = {0, 0, 0, 0, 0, 0, 0, 0};` 3.2 Data Transmission Implementation We defined a data structure IPH (Internal Packet Header), which includes attributes such as data type, length, and source card slot number. This header is used to encapsulate the message before data transmission, allowing the receiver to parse the header and differentiate the data based on the service type. The main IPH types include card configuration information, port registration information, routing information, and unknown data types. The `iph_attr` data structure is defined to distinguish different IPH_info types. Located at the beginning of the data packet, its data structure is as follows: `typedef struct _IPH_ATTR { u32 board_id; /*from which board*/ int iph_type; /*datagram type*/ unsigned long length; /*datagram length (without IPH)*/ }IPH_ATTR, *P_IPH_ATTR;` Different data structures are defined for each type of IPH information, and these are stored sequentially after the `iph_attr` structure in the data packet header. When sending data, the data is IPH-encapsulated, the destination PCI address is selected according to the aforementioned board address mapping table, and then the bus interface function is called to complete the data transmission. The sender notifies the receiver of the transmission address and data length information by writing to the mailbox register of the receiving board bridge chip, generating an interrupt to trigger reception. The PLX bridge chip supports direct access from the local bus to the PCI bus. It has eight mailbox registers, the first four of which can generate interrupts. Each mailbox is 32 bits. The transmission address and data length information are handled by mailbox i and mailbox i+4 respectively. When the receiver receives two parameters, an interrupt is generated to receive data [5]. This mechanism enables the receiving process to have four service windows, which improves the system throughput. When the mailbox of the receiving board PLX chip is written with parameters, a local interrupt is generated to check the "drawer". Before the interrupt is generated, the data has actually been sent to the target board. The interrupt service routine maintains a data queue for the receiving end. It reads the information in the mailbox, analyzes the address to find the corresponding data and hands it over to the bottom half for processing. The bottom half parses the IPH of the data packet to distinguish the data type. If it is configuration, port, routing and other information, it performs the corresponding configuration. If it is data information, it processes or forwards it. In summary, the system achieves PCI address space mapping between various boards through a "drawer mechanism" and the maintenance of several address tables. Boards can transmit data to the target board via the bus by writing data to the mapped address space, realizing cross-bus memory access. A custom IPH packet header distinguishes data types to assist in data information management, completing routing maintenance and the logical functions of the forwarding engine, achieving interference-free data transmission and effective communication management. 4. Summary and Outlook The author's innovation lies in presenting a CPCI-based distributed system design and proposing a message storage mechanism and address information maintenance strategy based on the "drawer mechanism." The CPCI-based distributed system described in this paper can achieve a 64-bit bus width and a peak bandwidth of 264MB/s. Each host in the system can independently complete data processing and communication, and can carry multiple services including voice and data. Users can also communicate via the PSTN network connected to the user access board and the voice service board, and the Internet connected to the data service board. It has significant application prospects in communications, military, and other fields. To make this communication system more practical on a large scale, future work includes: (1) implementing an easy-to-operate remote management system to monitor and allocate communication services; (2) designing CPCI interface cards that support more service types, such as xDSL, H.264, etc.; (3) conducting rigorous performance tests under conditions of significant external interference to prove that the system can meet the service requirements of telecommunications. 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