Abstract: This paper introduces a data acquisition system based on the Compact PCI bus, designed to meet the requirements of industrial control systems. This system can acquire analog, serial, and parallel digital signals. The hardware structure of the acquisition system and the implementation of the Compact PCI interface are discussed in detail, taking into account the performance characteristics of the DSP chip TSM320F2812 and the PCI interface chip PCI9054.
Keywords: Compact PCI; data acquisition; DSP
Abstract: In the view of requirements of Industrial Control System, this paper introduces a Compact PCI interface based data acquisition system, which provides acquisition channels for analog signals, serial and parallel digital signals. According to the functions and traits of Digital Signal Processor TMS320F2812 and PCI bus controller PCI9054, the hardware architecture and the realizing method of the Compact PCI interface is described in detail.
Key Words: Compact PCI; data acquisition; DSP
introduction
Real-time performance and reliability of data acquisition are crucial factors affecting the performance of industrial control systems. The data acquisition system's speed primarily depends on the A/D conversion rate, communication interface, and bus transmission rate. TI's TMS320F2812 DSP chip, with its high operating frequency and abundant peripheral resources, can meet the real-time requirements of acquisition systems while reducing system design costs. The Compact PCI bus, as an extension of the PCI bus to industrial control, possesses not only high-speed transmission rates but also excellent mechanical and electrical characteristics. This paper presents a data acquisition system based on the Compact PCI bus. The system uses a DSP as its control core and can perform analog signal acquisition, parallel interface, and serial interface data signal sampling.
1. Introduction to Compact PCI Bus
The Compact PCI bus is fully compatible with the PCI standard, but as an open industrial computer standard, it differs from the PCI bus in many ways. These differences are mainly reflected in:
(1) The Compact PCI bus has hot-swapping capability, which allows the damaged board to be replaced without power interruption, which is crucial for systems with high reliability requirements.
(2) The Compact PCI bus uses Eurocard, which has better mechanical characteristics. The assembly technology of Eurocard is now very mature. The vertical and parallel insertion of the card into the chassis is conducive to ventilation and heat dissipation. The use of plug-in power modules makes maintenance convenient and suitable for installation on standardized industrial racks.
(3) It uses a high-density pinhole bus connector, which is completely airtight and has higher shock resistance and reliability than the PCI slot of a desktop computer.
(4) The Compact PCI backplane can accommodate 8 cards, which is twice as many as the original PCI specification, and can better meet the needs of industrial systems.
2 Hardware Structure Design of the Data Acquisition System
In industrial control systems, the data acquisition system needs to transmit analog parameters such as motor speed and current loop to the monitoring host, while also acquiring various parameters and image data from the slave devices. Simultaneously, the monitoring host must send various control signals to the slave devices. To accommodate these diverse needs, the design incorporates both analog and digital acquisition methods, enabling 8-channel A/D sampling, 2-channel serial data acquisition, and 2-channel parallel data acquisition. The system's block diagram is shown in Figure 1.
Figure 1. Block diagram of the data acquisition system
The data acquisition system uses the TMS320F2812 digital signal processing chip as its control core. The F2812 has a maximum operating frequency of 150MHz and, in addition to abundant internal memory resources, also has various peripheral resources such as ADC, SCI, and SPI. The design utilizes its ADC and SCI modules for acquiring analog and serial digital signals. Parallel data acquisition bypasses the DSP and directly exchanges data with the host. Due to the speed mismatch between the host and peripherals, the dual-port RAM chip IDT70V24 is selected as the data buffer. It is a high-speed, low-power dual-port RAM with a storage capacity of 8KB. The system's logic control is implemented using the XC95108 CPLD chip, which is primarily responsible for PCI local bus arbitration and address decoding. The implementation of the three acquisition modules is as follows:
(1) A/D Acquisition Module. The analog signal sampling utilizes the built-in digital-to-analog converter (ADC) module of the F2812. This ADC has 16 analog input channels, two built-in sample-and-hold circuits (S/H), a conversion accuracy of 12 bits, a maximum conversion rate of 12.5 MSPS, and supports data input ranging from 0 to 3 V. The 16 input channels share a single analog-to-digital converter within the ADC. They are divided into two groups of eight channels each, and a sequencer is used to set the order in which each channel occupies the ADC. Eight of these channels (ADCIN0 to ADCIN7) are used in this design.
(2) Serial Data Acquisition Module. The F2812's SCI module has two serial communication interfaces, configurable to 65,536 different baud rates, with a parity check flag, and can operate in half-duplex or full-duplex mode. It can be set to interrupt or polling mode. In addition, the SCI has two enhanced features: ① Both sending and receiving have independent FIFOs with a FIFO depth of 16 words, and the trigger level can be configured to any number within 16. This flexible setting is very convenient for practical use, because the data length acquired by the lower-level machine is often not an integer multiple of 16. Setting the FIFO trigger level according to the data length can ensure that a frame of data is transmitted and processed in a timely manner; ② It can realize automatic baud rate detection, which is very suitable when the baud rate of the communication terminal is unknown or when the communication terminal needs to be replaced. The communication between the lower-level machine and the monitoring host uses an RS-422 interface, which has a long transmission distance and strong anti-interference capability. RS-422 transmission uses differential levels, while the input/output pins of SCI use TTL levels, requiring level conversion. The design selected the MAX3461 level conversion chip, which conforms to the RS-422 standard.
(3) Parallel communication module. For signals with large data transmission volumes, such as image signals, parallel communication is required. This acquisition system provides two parallel ports with a data width of 8 bits and an address width of 8 bits. They exchange data with the host through dual-port RAM.
3 Compact PCI Interface Design
3.1 CPCI Bridge Chip
Currently, many PCI protocol chips also support hot-swapping, making it easy to port existing PCI bus-based hardware systems to the CPCI architecture without major hardware and software modifications. This design uses the PCI9054 from PLX, which conforms to the PCI 2.2 specification and the CPCI 2.1 hot-swapping specification.
For CPCI's hot-swapping specifications, the PCI9054 provides the pins ENUM# and LEDon/LEDin. Activation of ENUM# indicates an impending change in the board's insertion/removal status. The LEDon/LEDin pins drive external LEDs to indicate the current connection and disconnection status of the system software layer. The PCI9054 also provides the Hot-Swapping Control Register HS_CSR to record board insertion/removal status and control indicator light status. The definition of HS_CSR is shown in Table 1. Table 1: Hot-Swapping Control Status Register HS_CSR
When the board is inserted, HS_CSR[3] is set to 1, the blue light is lit, and PCI9054 sets HS_CSR[7] to 1, activating the ENUM# signal to cause an interrupt. The interrupt is cleared after the device driver is installed, HS_CSR[3] is set to 0, and the blue light is turned off. When the board is removed, HS_CSR[6] is set to 1, activating the ENUM# signal to cause an interrupt. After the host uninstalls the driver, HS_CSR[3] is set to 1, the blue light is lit, indicating that the board can be safely removed.
3.2 Hot-swappable power management
The main signals used for hot-plug control in the CPCI specification are BD_SEL#, HEALTHY, and PCI_RST#. The pins of the CPCI bus connector J1 are divided into long pins, medium-long pins, and short pins. Long pins are for power and ground signals, medium-long pins are for PCI bus signals, and short pins are for BD_SEL# and IDSEL. When a card is inserted, the power signal contacts first, pre-charging the PCI bus signal to 1V. This is to reduce the impact on the PCI bus signal during hot-plugging. Then the PCI bus signal connects, and finally the BD_SEL# signal connects. A valid BD_SEL# indicates that the card is properly inserted and ready to power on. The card removal process is the reverse. HEALTHY# reflects the card's power status. PCI_RST# is the host reset signal, which, together with HEALTHY#, controls the reset signal of the PCI local bus.
The LTC1646 is a hot-swappable power management chip from Linear Technology for the CPCI interface. The LTC1646 requires two external N-channel transistors as switches to control the 3.3V and 5V power supply to the board. The LTC1646's OFF/ON# pin is connected to BD_SEL#; when BD_SEL# is low, the transistor is turned on, and the 3.3V and 5V power supplies are powered on at a certain rate. PWRGD# is connected to HEALTHY#; this signal is low when the board's power supply is within tolerance. PCI_RST# is connected to the LTC1646's RESETIN# pin; it is ORed with the HEALTHY signal to obtain the output signal RESETOUT#, which is connected to the PCI9054's RST# pin as the CPCI board's reset signal. The LTC1646 provides an output pin PRECHARGE, which is connected to the PCI9054's bus signal to pre-charge the bus signal during board insertion and removal. The signal that requires pre-charging needs to be pulled up to the pre-charging voltage (1V±10%) through a 10kΩ resistor.
4. Software Interface
Because industrial peripherals are diverse and the characteristics of the acquired signals vary, if the internal program of the hardware system is fixed in one mode, the optimal transmission effect will inevitably be lost. Furthermore, modifying the internal program of a hardware board after delivery is extremely cumbersome. Therefore, this system provides a software interface for application developers, allowing hardware configuration modifications to be made directly within the application interface without the need for a simulator.
Modification of hardware operating parameters is achieved through interrupts. A custom 16-bit control register, User_CSR, is used, with the high 4 bits for the command word and the low 12 bits for the control word. When the application writes data to User_CSR via the PCI bus, the CPLD sends an interrupt signal to the F2812's external interrupt pin XINT2 through its decoding logic. After responding to the interrupt, the F2812 reads the value of User_CSR, determines which parameter needs to be modified based on its command word, obtains the new parameter value based on its control word, and writes it to the corresponding register to complete the modification. Due to space limitations, only the modification of SCIA settings is used as an example to illustrate the specific implementation method. The definition of SCIA modification by User_CSR is as follows:
Table 2 Partial Definitions of User_CSR
The hardware configurations that can be modified through this interface include the SCI baud rate, the trigger level of the transmit and receive FIFOs, and the amount of dual-port RAM space occupied by each acquisition channel.
5. Conclusion
This design uses the TMS320F2812 as the control core of the data acquisition system, meeting the system's real-time requirements while saving peripheral resources and improving the system's cost-effectiveness. Applying the Compact PCI bus to the acquisition system enables hot-swappable operation, improving overall system reliability and making it more adaptable to industrial environments. The innovation of this paper lies in combining the advantages of the Compact PCI bus and DSP chips, significantly improving system reliability and real-time performance, while also providing application developers with a good interface, facilitating the modification of hardware operating parameters and enhancing system flexibility.
References:
[1]PCI9054 Data Book V2.1,PLX Technology Inc,January,2000
[2]TMS320F2810,TMS320F2812 Digital Signal Processor Data Manual, Texas Instruments Inc, April, 2001
[3]LTC1646 Compact PCI Dual Hot Swap Controller, Linear Technology Inc, 2002
[4] Wang Nianxu, DSP Fundamentals and Application System Design, Beijing: Beijing University of Aeronautics and Astronautics Press, 2001
[5] Liu Ying, Luo Jiarong, Meng Yuedong, Design of a monitoring system based on Compact PCI bus, Microcomputer Information, 2004, No. 1
