Abstract: This paper first briefly introduces the communication requirements between the speed measurement and positioning unit and the on-board equipment in a high-speed maglev train, and based on this, proposes an implementation method for synchronous communication based on the RS485 physical layer. The Xilinx XC2S100 is used as the transceiver, and the TI TMS320F2812 is used as the controller. The system hardware and software design scheme is formulated, and the feasibility of the scheme in practical applications is verified through simulation and experiments. Keywords: Maglev train; RS-485; synchronous communication Abstract: This paper firstly introduces the communication requirements between the locating electronic unit and onboard equipment of a high-speed maglev train. A synchronous communication method based on the RS-485 physical layer is presented to fulfill these requirements. Xilinx's XC2S100 is used as the communication transceiver and TI's TMS320F2812 is used as the communication controller. The hardware and software scheme are designed, and its feasibility in practical applications is verified by simulation and experiment. Keywords: Maglev train; RS-485; synchronous communication 0 Introduction In a high-speed maglev transportation system, the onboard speed and positioning unit measures the vehicle's position and speed in real time and transmits the position and speed signals to the ground-based traction control system and operation control system via a radio system. This is used for feedback control of the long-stator linear synchronous motor traction and for command and safety protection of vehicle operation. The speed and positioning unit is the core and key to the closed-loop control of the traction and operation control system. The speed measurement and positioning unit is located adjacent to the levitation electromagnet, long stator windings, and iron core, situated within a levitation magnetic field and traction magnetic field. The electromagnetic environment is extremely complex, placing high demands on the electromagnetic compatibility performance of its communication equipment. Furthermore, to meet the requirements of the traction control system, the accuracy of the speed measurement and positioning signal is extremely high. Therefore, the speed, real-time performance, and reliability of the speed measurement and positioning signal transmission are all critically important. 1. Implementation Method of Synchronous RS-485 Considering the working environment and communication function requirements of the speed measurement and positioning unit, after analysis and comparison, a synchronous communication method with a higher transmission rate was chosen when selecting its communication method with the vehicle-mounted radio system. A well-shielded twisted-pair cable was used to implement RS-485 balanced differential transmission. 1.1 Interface Design and Communication Protocol The communication interface relationship between the speed measurement and positioning unit and the vehicle-mounted radio control unit is shown in Figure 1. The vehicle-mounted radio control unit is the master controller, and the vehicle speed measurement and positioning unit is the controlled party. Both communicating parties consist of transceivers and controllers. The transceivers use an RS-485 synchronous serial interface, with each interface having four pairs of differential lines. [align=center]Figure 1. Schematic diagram of communication interface relationship[/align] In Figure 1, CLK is the clock signal, ANF is the radio request signal, UEF is the gating signal, and DATA is the data signal. The vehicle speed measurement and positioning unit sends data to the radio control unit every 20ms, with a transmission rate of 512kbps. To prevent small pulses from interfering with the signal, the width of the ANF signal is 10 CLK signals; after the ANF signal goes low, it waits for 10 CLK signal widths before the UEF signal becomes active. The ANF, UEF, and DATA signals all change on the rising edge of CLK. When there is no signal transmission, UEF, DATA, and ANF are all low, and the clock signal continues to transmit. During data transmission, a left-shift method is used, that is, the high-order bits are transmitted first, followed by the low-order bits. The information frame format is shown in Table 1: Table 1 Information frame format 1.2 Implementation of synchronous 485 transceiver In the communication system discussed in this paper, both the vehicle speed measurement and positioning unit and the vehicle radio control unit use Xilinx's XC2S100 as the transceiver for communication to simulate the synchronous 485 transmission and reception timing. The FPGA design of synchronous 485 is mainly based on Verilog hardware description language, and the EDA tools used include ISE (including its internal integrated tools) and Modelsim. (1) Generation of clock and timing signals: For the vehicle radio control unit, a 512k clock signal and an ANF (radio request) signal every 20ms are required. In addition, when the unit receives positioning data serially, its receiving clock should be 16 times 512k (baud rate clock), that is, 8M. Therefore, frequency dividers are widely used in synchronous 485 communication. 1) Even frequency division is relatively simple. Just design a counter to count, and flip the clock level after frequency division when the count reaches half of the divided number; odd frequency division is more complicated because the counter cannot count non-integers and a certain algorithm is required. The waveform of the odd frequency division module after functional simulation is shown in Figure 2: [align=center] Figure 2 Simulation waveform of frequency division module[/align] 2) Generation of ANF signal: The ANF signal is sent once every 20ms, and the pulse width of each transmission is 10 clock cycles. The generation of ANF signal can be divided into two parts. First, a pulse signal is generated every 20ms, and then the width of this pulse signal is changed to 10 clock cycles. (2) Transmission and reception of serial data 1) Generation of serial data: According to the requirements of the communication protocol, the speed measurement and positioning unit should serially shift out 72 bits of data every 20ms. If one bit is shifted out every transmission clock cycle, it will take 72 clock cycles to shift out all of them. Therefore, the gate signal also needs to maintain a width of 72 clock cycles. 2) Serial Data Reception: Synchronous serial reception of a frame (72 bits) of data differs from asynchronous serial reception. Since the transmit and receive clocks are not asynchronous, the first low level after the idle state cannot be used as the start of a frame; instead, the rising edge of the gate signal (UEF) is used to determine the arrival of a data frame. To avoid glitches during data transmission, reception is still performed at 16 times the baud rate clock, meaning sampling occurs every 16 baud rate clock cycles. Therefore, each data bit will be sampled at the midpoint of its transmitted value. The simulation timing diagram for serial data transmission and reception is shown in Figure 3. [align=center] Figure 3 Synchronous 485 Simulation Timing Diagram[/align] 1.3 Data Exchange Between Transceiver and Controller The synchronous communication timing based on RS-485 is simulated using an FPGA as the communication transceiver, but the communication data is ultimately exchanged with the system's CPU. In this communication design, both communicating parties use TI's TMS320F2812 as the processor, i.e., the communication controller. Data exchange between the FPGA and DSP must meet certain timing requirements to ensure that the speed positioning unit transmits position and speed signals to the vehicle radio control unit in real time. In this system, the DSP controller is designed using C language. (1) Data exchange between the DSP and FPGA on the speed positioning unit side The external address spaces available for the external memory XINTF of the TMS320F2812 are XINTF0, XINTF2, and XINTF6. XINTF0 uses XZCS0AND1 as the chip select signal, and the external memory expansion space is 8K; XINTF2 and XINTF6 use XZCS2 and XZCS6AND7 as chip select signals, respectively, and the external memory expansion space is 0.5M for each. When the speed positioning unit sends position and speed information, it transmits it to the FPGA through the DSP's data line. The DSP finds the corresponding address according to the corresponding external memory chip select signal and writes it to the address after obtaining new positioning data from the underlying sensor. The corresponding hardware connection diagram is shown in Figure 4: [align=center] Figure 4 Hardware connection diagram of the vehicle speed measurement and positioning unit DSP controller writing data to the FPGA transceiver[/align] According to the protocol requirements, each transmission of positioning information includes 5 bytes of user data and 2 bytes of CRC checksum. Therefore, the 16-bit data line needs to be transmitted at least four times to completely transmit the underlying positioning information to the FPGA. To reduce hardwiring, only the high five bits of the address lines are connected here, and the low four address lines are decoded from 4 to 16. The highest address line is used as the enable signal for the decoder. Take the four addresses corresponding to an external memory chip select signal. For example, when the chip select signal XZCS2 is low (corresponding external memory address range: 0x080000—0x100000), the addresses 0xe0000, 0xe4000, 0xe8000, and 0xec000 can be used as the addresses for the DSP to write data to the FPGA. Since each different address corresponds to an address decoding value, a location information transmission can only be considered complete when all four decoding values ​​appear. At this time, the seven consecutively received bytes plus the frame header and frame tail are sent as a frame of data to the vehicle radio control unit as a speed measurement and positioning unit. The corresponding address decoding values ​​are shown in Table 2. Table 2 Address decoding values ​​(2) Data exchange between DSP and FPGA on the vehicle radio control unit side Since the sampling time is in milliseconds, in order to avoid occupying too much CPU resources, the DSP in the vehicle radio control unit does not use the polling method when reading data from the FPGA, but uses an external interrupt to receive data. Connect the DSP's 16-bit data line to the FPGA, and the DSP's XINT1 is also connected to the FPGA's I/O pin. If XZCS0AND1 is selected as the external memory chip select signal, the address space range for the DSP to read data from the FPGA is 0x002000-0x004000. The data read in this address range is the positioning data transmitted to the DSP on the data line. The corresponding hardware connection diagram is as follows: [align=center] Figure 5 Hardware connection diagram of the DSP controller of the vehicle radio transmission unit reading data from the FPGA transceiver[/align] Since a frame of data transmitted from the FPGA to the DSP is 72 bits, it needs to be transmitted in 5 parts through the 16-bit data line. An external interrupt is generated every time 16 bits of data arrive. Assuming the baud rate clock is 512k, and assuming that a complete frame of data from the positioning unit is 0x02123456789abcde03, the data forwarded by the vehicle radio unit to the DSP through the 16-bit data line is 0x0002, 0x1234, 0x5678, 0x9abc, 0xde03. The timing of data and interrupt signal generation is shown in Figure 6. As can be seen from Figure 6, each time a dataout occurs, an external interrupt signal xint1 is issued accordingly. Once the DSP receives the external interrupt, it reads the signal value from the 16-bit data line in the interrupt service subroutine. To receive a complete frame of signal, a 16-level FIFO can be defined in the external interrupt service routine. When the data read from the bottom layer of the FIFO is 0x02, the start of a frame of data can be determined (if 0x02 exists in the user data and checksum, corresponding character escaping is required). Receiving the following data sequentially yields a complete frame of positioning information. [align=center] Figure 6 Simulation waveform of the vehicle radio transmission unit DSP controller reading data from the FPGA transceiver[/align] 2 Schematic diagram of the two communicating parties Based on the above description of the synchronous 485 implementation method, the top-level schematic diagram drawn using the ECS tool in ISE is as follows, including the synchronous data transmission of the speed measurement and positioning unit and the synchronous data reception of the vehicle radio control unit. The schematic diagram of the synchronous data transmitter of the positioning and speed measurement unit is shown in Figure 7. [align=center] Figure 7 Schematic diagram of the synchronous data transmitter[/align] In Figure 7, addr_decode is the address decoding module, used to receive a complete frame of positioning information from the DSP; tra485data is the serial data and gate signal transmission module. In this circuit, din (15:0) comes directly from the DSP's 16-bit data lines; addr (3:0) is connected to the DSP's A17-A14 address lines; and clkin and anfin signals are provided by the vehicle radio control unit. The output dataout and uefout are sent to the vehicle radio control unit after being buffered and differentially converted. The schematic diagram of the synchronous data receiver of the vehicle radio control unit is shown in Figure 8. [align=center] Figure 8 Schematic diagram of synchronous data receiver[/align] In Figure 8, divide_512k is the transmit clock generation module, which generates the baud rate clock required for communication; anf_shift is used to generate the radio request signal; rec485data is used to serially receive positioning information and forward it to the communication controller through the dataconvert module. In this circuit, Dataout (15:0) is directly connected to the DSP through the data lines, while Xint1 is connected to the DSP's external interrupt 1. anfout and clkout are obtained by dividing the input crystal oscillator frequency, and are sent to the vehicle speed measurement and positioning unit after being buffered and differentially converted. 3 Conclusion In the special communication environment of high-speed maglev trains, the synchronous communication method based on RS-485 physical layer has shown its advantages such as strong anti-interference, good real-time performance, and low bit error rate. Moreover, the implementation principle is simple and the hardware connection is not complicated. The communication transceiver implemented by FPGA is flexible and reliable. Its function has been verified in practical applications and the effect is good. References: [1] Zhang Weining. CPU and peripherals of TMS320C28x series DSP (Volume 1) (Volume 2) [M]. Beijing: Tsinghua University Press, 2005.1. [2] Wang Cheng, Xue Xiaogang. FPGA/CPLD design tool - Xilinx ISE usage details [M]. Beijing: Posts & Telecom Press, 2005.1. [3] Li Chaoqing. PC and single-chip microcomputer data communication technology [M]. Beijing: Beijing University of Aeronautics and Astronautics Press, 2000.12.