This paper introduces an electrocardiogram (ECG) data acquisition system designed using the C8051F206 microcontroller, and provides its detailed hardware and software configuration. The system features high accuracy, low noise, high common-mode rejection ratio (CMRR), and strong anti-interference capabilities, making it practically applicable. Electrocardiography (ECG) is a commonly used auxiliary tool in clinical disease diagnosis. The ECG data acquisition system is a key component of the ECG examination instrument. The main frequency range of human ECG signals is 0.05–100 Hz, with an amplitude of approximately 0–4 mV, making the signal very weak. Because ECG signals are usually mixed with other bioelectrical signals, and are further affected by external electromagnetic interference, primarily from a 50 Hz power frequency field, the background noise of ECG signals is strong, and the measurement conditions are complex. To detect clinically valuable clean ECG signals without distortion, the ECG data acquisition system is often required to possess high accuracy, high stability, high input impedance, high common-mode rejection ratio, low noise, and strong anti-interference capabilities. This paper utilizes the on-chip A/D converter and multiplexer of the C8051F206 to design a multi-channel ECG data acquisition system that meets the above requirements. 1 System Structure and Signal Conditioning Figure 1 shows a block diagram of an ECG data system. The ECG signal is picked up by a dedicated electrode and sent to a preamplifier for initial amplification. After suppressing various interference signals, it is sent to a bandpass filter to filter out interference signals outside the ECG frequency range. The main amplifier further amplifies the filtered signal to a suitable range, and then filters out power frequency and electromyographic interference using 50Hz and 35Hz notch filters. Finally, the qualified ECG analog signal is sent from the analog input terminal to the on-chip ADC of the C8051F206 for high-precision A/D conversion and data acquisition and storage. 1.1 Preamplifier Circuit Preamplification is a crucial step in ECG data acquisition. The specific circuit is shown in Figure 2. Because human electrocardiogram (ECG) signals are extremely weak, with strong background noise and high source impedance, and the polarization voltage difference introduced by the electrodes is large (hundreds of times larger than the ECG difference), preamplifiers typically require high input impedance, high common-mode rejection ratio (CMRR), low noise, low drift, low nonlinearity, suitable frequency band, and dynamic range. Differential amplifier circuits are generally used in their design. This design selects the instrumentation amplifier AD620 as the preamplifier. The AD620 employs ultra-β processing technology at its input, featuring low input bias current, low noise, high precision, long settling time, and low power consumption. Its CRR can reach 130 dB, making it highly suitable for use as a preamplifier in medical instruments. Its gain is adjustable (ranging from approximately 1 to 1000 times) and can be determined using the formula G = 1 + 49.4 kΩ/Rg. To prevent the preamplifier from operating in the saturation or cutoff region, its gain should not be too high. Experiments show that a gain of around 10 times is optimal. U3 can detect the common-mode signal of the human body on R2 and R3, which is then used to drive the shielding layer of the conductor to eliminate distributed capacitance and improve input impedance and common-mode rejection ratio. The "floating ground" drive circuit composed of U4, R5, R6, and C1 can invert and amplify the common-mode signal of the human body to excite the right leg of the human body, thereby reducing or even canceling the common-mode voltage, so as to achieve a strong suppression of 50Hz power frequency interference. U1 and U2 are mainly used to stabilize the input signal and improve the input impedance, further improving the common-mode rejection ratio. 1.2 Bandpass filter and main amplifier circuit As shown in Figure 3, the bandpass filter is composed of dual operational amplifier integrated circuit OP2177. OP2177 has the characteristics of high precision, low bias, and low power consumption. It integrates two operational amplifiers on the chip and can be flexibly composed of various amplification and filtering circuits. Since the frequency band of ECG signals is mainly concentrated around 0.05–100 Hz, which is relatively wide, two op-amps of OP2177 are used to design second-order voltage-controlled active high-pass and low-pass filters, which are then combined to form a bandpass filter. U6A, C6, C7, R8, and R9 constitute the high-pass filter; to avoid loss of the low-frequency components of the ECG signal, its cutoff frequency is designed as f = 1/(2π * C6 * C7 * R8 * R9) / 1/2 = 0.03 Hz. U6B, R10, R11, C8, and C9 constitute the low-pass filter; similarly, to avoid loss of its high-frequency components, its cutoff frequency is designed as f = 1/(2π * C8 * C9 * R10 * R11) / 1/2 = 130 Hz. The main amplifier circuit consists of OP1177 (U7), R12, and R13. Considering that the amplitude of the ECG signal is approximately 0-4mV, while the A/D conversion input signal requires approximately 1V, the amplification factor of the entire signal circuit needs to be around 1000 times. The preamplifier is approximately 10 times, therefore the amplification factor of this stage is designed to be around 100 times, i.e., G = 1 + R12/R13 ≈ 100. 1.3 Notch Filter and Level Boosting Circuit Power frequency interference is the main interference in the ECG signal. Although the preamplifier circuit has a strong suppression effect on common-mode interference, some power frequency interference enters the circuit as differential-mode signals, and the frequency is within the ECG signal frequency band. Combined with factors such as electrode and input circuit instability, the ECG signal output from the preamplifier circuit still has strong power frequency interference, so it must be specifically filtered out. The frequency characteristics of conventional active notch filters are quite sensitive to the parameters of circuit components, making precise adjustment difficult, and the circuit stability is not high. Switched-capacitor integrated filters do not require external resistors or capacitors to determine the frequency; the filtering frequency is determined solely by the external or internal clock frequency. Furthermore, their frequency characteristics are insensitive to clock and peripheral circuit parameters, resulting in stable performance. Linear Technology's LTC1068-50 integrated switched-capacitor filter integrates four independent second-order switched-capacitor filters with a clock-to-center frequency ratio of 50:1 and an error of ±0.3%. It can be powered by ±5V or 5V. Therefore, using the manufacturer's FilterCAD filter design software, it can be flexibly configured into various filters (low-pass, high-pass, band-pass, all-pass, etc.). To effectively filter out power frequency interference, this design utilizes the advantages of the LTC1068-50 to specifically design an 8th-order Butterworth 50Hz notch filter, using a 2.5kHz clock signal. The circuit design is shown in Figure 4. Testing showed a notch depth of up to 50dB and attenuation of approximately 100 times, achieving satisfactory results. Furthermore, electromyography (EMG) in the human body can interfere with ECG signals to varying degrees due to individual differences, sometimes even drowning out the ECG signal, thus requiring suppression. Studies have shown that EMG interference is mainly concentrated around 35 Hz. Therefore, this system also designed a 35 Hz infinite gain multiple feedback second-order notch filter, as shown in Figure 5. This second-order notch filter consists of U10A and U10B. Its cutoff frequency is approximately 35 Hz, and Q is approximately 7, which meets practical requirements. After a series of signal conditioning steps, the ECG signal output by the notch filter is an alternating signal. However, the input voltage range of the ADC built into the microcontroller in this system is 0–3.3V. Therefore, level boosting is required before sending the signal to the ADC. In Figure 5, the level boosting part consists of U11, R42, R43, and R44. The ECG signals of the 12-channel ECG data acquisition system can be obtained from different parts of the human body surface. Since all signals have the same frequency characteristics and only differ in waveform shape, the same signal conditioning circuit can be used for each signal. 2. Design of the Microcontroller Acquisition System 2.1 Data Acquisition System Based on C8051F206 Figure 6 shows the block diagram of the connection between the microcontroller and the signal conditioning circuit. The C8051F206 is a mixed-signal ISP Flash microcontroller produced by Cygnal. This chip contains a high-speed microcontroller core fully compatible with the 8051, 8k Flash, 4-byte wide I/O ports, hardware UART and SPI buses, a 12-bit high-precision ADC, and up to 32 channels of analog input multiplexers. Each I/O pin can be configured as an analog input port using software, with a conversion rate of up to 100ksps. These features make the C8051F206 very suitable as the controller for this data acquisition system. According to system requirements, ports P1.0~P1.7 and P3.0~P3.3 can be configured as input terminals for 12 channels of ECG analog signals. In addition, the C8051F206 provides a 2.5kHz clock signal for the 50Hz notch filter. 2.2 Software Design After system power-on, initialization settings must be performed first, including system reset mode, clock source, voltage reference, interrupts, UART, SPI, ADC settings, and configuration of I/O ports using crossbar switches. These settings can be made by configuring the corresponding special function registers (SFRs). For details, please refer to relevant documentation. This system selects an internal clock source with a frequency of 16MHz and uses an internal voltage reference VDD. Since the main frequency range of ECG signals is 0.05~100Hz, according to the sampling theorem, to ensure signal acquisition without distortion, the sampling frequency is set to 200Hz, i.e., the sampling period for the 12-channel ECG data is 5ms. Therefore, the ADC conversion clock is set to a 16-fold division of the system clock. The startup method combines Timer 2 overflow and software write to the ADBUSY bit. Conversion uses a polling method, and the completion of an A/D conversion is determined by reading the ADBUSY bit of the ADC0CON control register. The converted data result is right-aligned, and the 12-bit data result word is read into FLASH from the data word register. 3. Conclusion Compared with conventional designs, this system features stable performance, high accuracy, and strong anti-interference capabilities, especially good suppression of 50Hz power frequency interference. It can acquire high-quality ECG signals reflecting ECG characteristics and their changing patterns. The design fully utilizes the on-chip 12-bit ADC resources of the high-performance microcontroller C8051F206 to simplify the system structure. The acquired data can be flexibly and conveniently sent to the ECG processing center for subsequent analysis and processing via the C8051F206's SPI port. Editor: He Shiping