In data acquisition and measurement instruments, especially portable devices, data storage and transmission are unavoidable issues. In recent years, TI's low-power microcontroller MSP430 has brought about a significant revolution in instrument design and manufacturing. The application of new controllers and large-capacity serial memories has greatly improved product performance. This article mainly addresses two issues: 1. Solving the data interface problem between the data acquired by the MSP430 and the EEPROM24C256, i.e., the data storage problem; 2. Solving the data communication problem between the EEPROM and the host computer (ordinary microcomputer), i.e., the data upload problem after storage. First, a brief introduction to the main integrated circuits is given. [b]Introduction to MSP430F449[/b] The MSP430F449 is one of the MSP430 series, a 16-bit microcontroller characterized by high integration, rich functionality, and low power consumption. Its integrated debugging environment, Embedded Workbench, provides a good C language development platform. Based on the complexity and large program capacity requirements of the design, the MSP430F449 was chosen. This chip has 64K of program memory, which can meet the needs of most complex control applications. Its 100-pin QFP package offers good interchangeability, and its pinout is identical to chips such as the MSP430F437 and MSP430F435, allowing for reasonable selection of program size. The 24C256 is a serial EEPROM supporting the I2C protocol with a capacity of 32768 bytes. The above is the pinout diagram of the 24C256. A0, A1, and A2 constitute the physical address of the memory, serving as the control address to distinguish different memories on the I2C bus. Up to eight devices can be connected simultaneously on the I2C bus. WP is write protection; a high level will disable write operations on the device. SCL and SDA are the control lines for data transmission. SCL is the clock signal, and SDA is a bidirectional data line used to complete data writing and reading. Data transmission is completed in conjunction with the clock signal SCL according to the requirements of the I2C protocol. CP2102 Introduction: The CP2102 is a USB-to-UART bridge circuit that converts USB data to UART data. It features simple circuit connection, reliable data transmission, and converts serial data from the lower-level machine into USB data format for convenient data communication. On the upper-level computer, the chip's driver allows for simple serial port read/write operations on the USB data. Programming is simple and operation is flexible. The above is the interface schematic diagram of the MSP430F449, EEPROM, and CP2102. This article focuses on the data storage and transmission after the data acquisition process is completed. Data acquisition is diverse. Analog quantities can be acquired through the on-chip ADC converter, or data can be converted from special sensors such as temperature and pressure sensors through independent port control lines. These are not covered in this article. This article mainly focuses on the storage and transmission processing of data after different acquisition processes. The Objective Requirements of Automatic Data Storage : In many measurement processes, it is not only necessary to read simple instrument values, but also to scientifically analyze and process data over a period of time to achieve predictive and analytical purposes. In such cases, long measurement times and automated data acquisition without manual intervention are required, necessitating automatic data storage. Another reason is the high frequency of data acquisition, where human observation alone cannot meet practical needs, necessitating effective data storage. Integrated Circuit Selection : Many high-capacity FLASH chips are widely used, but these chips have numerous I/O lines, requiring significant controller resources. In situations with numerous peripheral devices and complex interfaces, especially in portable instruments with comprehensive functions and small size, a serial EEPROM with an I2C interface becomes the optimal choice to simplify peripheral circuitry without compromising storage capacity. 24C256 Program Control Principle: The 24C256 is a 512x64 memory with an I2C interface. Besides adhering to the necessary logic of the I2C protocol during data storage, a crucial and easily overlooked issue that leads to errors is the storage address. The 24C256 has a data capacity of 32768, which is the number of effective bytes it can store. Therefore, its address is a 16-bit integer with a valid range of 0 to 32768. Data is stored in bytes, with only 15 bits of data being valid within the 16-bit address. The lower 6 bits (0-5) represent a capacity of 0-63, and the next 9 bits (6-14) represent a page number ranging from 0 to 511. During contiguous data storage, the storage address automatically accumulates within the same page. However, when data is stored on different pages, the address does not automatically accumulate. If not handled correctly, the data will restart from the current page address, overwriting any existing data. For example, address 63 (binary code 111111) represents the last storage space on page 0, and address 64 (binary code 1,000000) represents the first storage space on page 1. If the device is in contiguous storage mode when the current storage address is 63, data errors will occur. Why? The 24C256 supports contiguous data storage, with a maximum storage size of 64 bytes (one page). If the address selection exceeds this limit, the data will overwrite the beginning of the current page and be re-stored, causing data errors. In practice, although data is stored in pages, it is sequential in form, so there's no need to specifically distinguish between page addresses and intra-page addresses. Even in contiguous storage, data errors can still occur even if the amount of data stored each time is less than 64 bytes. For example, if the amount stored each time is 11 bytes, and the address changes from 0, 11, 22, 33, 44, 55, 66… it seems fine, as the address increments by 11 each time. However, the storage result is still incorrect. Why? Because the space starting at address 55 cannot provide 11 consecutive intra-page storage spaces. When the address increases to 63, the data restarts from address 0 of that page, leading to data storage errors. An effective solution is that if using contiguous storage mode, the address arrangement should ensure that the storage block size is 64, 32, 16, 8, 4, 2 bytes. Otherwise, contiguous address storage should not be used. If the number of valid data bits in the data acquisition is less than 64, for example, if the result of each acquisition is 30 bytes, it should be stored in units of 32 in continuous storage mode, and the missing bytes should be padded with zeros. The following is the basic control module for data transmission of the 24C256: Delay processing module: void IIC_Delay(void) { _NOP(); _NOP(); _NOP(); } Start I2C module: void start_IIC(void) // Start I2 { P2OUT&=0xf9; // Set P2 output P2DIR&=0XFD; //SDA=1, pull-up resistor makes P2.1 H, FD=1111,1101 P2DIR&=0XFB; //SCL=1 FB=1111,1011 P2DIR|=0X02; // SDA=0 P2DIR|=0X04; // SCL=0 } Stop I2C module: void stop_IIC(void) // { P2DIR|=0X02;//SDA=0 IIC_Delay(); P2DIR&=0XFB;//SCL=1 FB=1111,1011 P2DIR&=0XFD;//SDA=1, Pull-up resistor makes P2.1 H, FD=1111,1101 IIC_Delay(); P2DIR|=0X04;// SCL=0 } ? Send "0" module void send_zero(void) // { P2DIR|=0X02;// SDA=0 IIC_Delay(); P2DIR&=0XFB;//SCL=1 FB=1111,1011 IIC_Delay(); P2DIR|=0X04;// SCL=0 } ? Send 1 module void send_one(void) // { P2DIR&=0XFD;//SDA=1, pull-up resistor makes P2.1 H, FD=1111,1101 IIC_Delay(); P2DIR&=0XFB;//SCL=1 FB=1111,1011 IIC_Delay(); P2DIR|=0X04;//SCL=0 } ? Send single character data void send_char(unsigned char data_out) // { unsigned char i,tmp=0x80; for (i=0;i<8;i++) { if ((data_out & tmp)>0) send_one(); else send_zero(); tmp/=2; } } ? Read single character data unsigned char read_char(void) { unsigned char i,tmp=0x80; unsigned char data1=0; for (i=0;i<8;i++) {P2DIR&=0XFD;//SDA=1, 11111101 IIC_Delay();// P2DIR&=0XFB;//SCL=1 FB=1111,1011 IIC_Delay(); if（（P2IN&0x02）>0x00） ｛ data1|=tmp; ｝ P2DIR|=0X04;// SCL=0 IIC_Delay(); tmp/=2; ｝ return data1; ｝ ? Check the response signal module void iic_ACK (void) ｛ ack_flag=0x00; P2DIR&=0XFD;//SDA=1, FD=1111,1101 IIC_Delay(); P2DIR&=0XFB;//SCL=1 FB=1111,1011 IIC_Delay(); while((P2IN&BIT1)==BIT1); P2DIR|=0X04;//SCL=0 IIC_Delay(); } ? Reject acknowledgment module void iic_NACK(void) { P2DIR&=0XFD;//SDA=1, IIC_Delay(); P2DIR&=0XFB;//SCL=1 FB=1111,1011 IIC_Delay(); P2DIR|=0X04;//SCL=0 IIC_Delay(); P2DIR|=0X02;//SDA=0 IIC_Delay();// } ? Write continuous data module void WriteNbyte(unsigned char *p, unsigned int addr, unsigned char number) {start_IIC(); send_char(0xa2); iic_ACK(); send_char(addr/256); //high address byte iic_ACK(); send_char(addr%256); iic_ACK(); do {send_char(*p); p++; iic_ACK(); } while(——number); stop_IIC(); delay(10);} ? Send response module: ACK (LOW) void S_ACK (void) {P2DIR|=0X02;// SDA=0 IIC_Delay(); P2DIR&=0XFB;//SCL=1 FB=1111,1011 IIC_Delay(); P2DIR|=0X04;// SCL=0 IIC_Delay(); } The `void ReadNbyte(unsigned char *p, unsigned int addr, unsigned char number)` module continuously reads characters. Its code snippet is as follows: `{ start_IIC(); send_char(0xa2); iic_ACK(); send_char(addr/256); iic_ACK(); send_char(addr%256); iic_ACK(); start_IIC(); send_char(0xa3); iic_ACK(); do { *p=read_char(); p++; if(number!=1) S_ACK(); //send ACK } while(--number); iic_NACK(); stop_IIC(); }` This module transmits data. Data transmission is an effective way for data stored in EEPROM to reach the computer. The most common method for uploading data to a computer is via a serial (RS232) interface. Now, with the continuous development of USB, data transmission can be achieved conveniently and quickly via USB, meeting the requirements of speed and device appearance. However, USB driver design is a relatively complex task. This example uses a simple bridging circuit to directly convert data from the UART interface to USB via a CP2102 bridge. Data output from the 430F449 asynchronous serial port is automatically converted to USB-compliant data and directly connected to the computer's USB port. The host computer application can directly read and write port data like a serial port using the CP2102 driver. Conclusion: The above hardware design is relatively simple and reliable and can be directly applied to similar control chips. The software code also has good portability, as long as the control clock and data port settings are consistent with the program software. References: 1. *MSP430 Series 16-bit Ultra-Low Power Microcontroller Practice and System Design*, Tsinghua University Press; 2. *MSP430 Series Microcontroller Interface Counting and System Design Examples*, Beijing University of Aeronautics and Astronautics Press; 3. *MSP430 Series Microcontroller C Language Programming and Development*, Beijing University of Aeronautics and Astronautics Press. Editor: He Shiping