Abstract: This paper presents the implementation method of phase-locked frequency multiplication circuit in active power filter. The designed phase-locked frequency multiplication circuit can achieve signal frequency multiplication quickly and accurately, laying the foundation for starting DSP and realizing accurate signal sampling. Key word: active power filter; phase locking; frequency doubling Active power filter (APF) is a power electronic device that dynamically suppresses harmonics and compensates for reactive power . The phase-locked frequency multiplication circuit is an important component of the harmonic detection module of the active power filter, and its stability plays a key role in the fast response of the active power filter. The signal frequency of the power supply system varies over a wide range with changes in load. To achieve accurate signal sampling, the DSP must accurately know the current signal frequency to ensure that the sampling frequency is consistent with the signal frequency. The phase-locked loop (PLL) frequency multiplier circuit divides a complete cycle into N equal parts as the DSP's sampling signal. 1. Principle of the Phase-Locked Loop Frequency Multiplier Circuit The ability of the PLL to output a stable 12.8kHz square wave in real time is crucial for the entire detection module to start working in the shortest possible time after power-on. Figure 1 shows the principle block diagram of the PLL. [align=center] Figure 1. Principle Block Diagram of the Phase-Locked Loop Frequency Multiplier Circuit[/align] As can be seen from Figure 1, the PLL is a closed-loop frequency feedback system, mainly composed of a phase detector, a low-pass filter, a voltage-controlled oscillator, and an accumulator counter. The phase detector is a circuit that establishes a definite relationship between the output voltage and the phase difference between two input signals. It is one of the basic components of a phase-locked loop (PLL). Phase detectors can be divided into analog phase detectors and digital phase detectors. The output signal of the phase detector contains many harmonic components. When the phase-locked loop (PLL) is locked, the first term of these components is the "DC" component, and the other frequency components are unwanted signals. Furthermore, high-frequency noise interferes with the signal transmission in the PLL frequency multiplier circuit, and these higher-frequency components are also unwanted signals, so a low-pass filter is used to remove them. In this design, a first-order low-pass filter is used. A voltage-controlled oscillator (VCO) is an oscillator circuit whose output frequency corresponds to the input voltage. In automatic frequency control loops and PLL loops, the input control voltage is the error signal voltage, and the VCO is a controlled component in the loop. In the APF detection system, the output of the PLL frequency multiplier circuit serves as the signal to start AD sampling. The frequency divider divides the frequency of the output signal generated by the VCO by N. This factor is usually variable or programmable. The frequency divider is typically composed of cascaded flip-flops (such as RS flip-flops, JK flip-flops, or T flip-flops). One JK flip-flop can divide the clock input signal by 2, two flip-flops by 4, and so on. In this circuit, a binary adder counter CD4040 is used, meaning its accumulated number is always a multiple of 2. To obtain a multiplier of 256, the output signal is output from its Q8 pin. 2. Design of Phase-Locked Frequency Multiplier Circuit 2.1 Zero-Crossing Detection Circuit The schematic diagram of the zero-crossing detection circuit is shown in Figure 2. The circuit uses a Yubo CHV-25P Hall voltage sensor. The rated current of this Hall voltage sensor is 10mA, and the primary-to-secondary turns ratio is 2500:1000. Therefore, before connecting the A-phase grid voltage to the Hall voltage sensor, a current-limiting resistor is needed to limit the current to prevent excessive current from burning out the Hall voltage sensor. Its M terminal is the secondary current output terminal, and a sampling resistor needs to be added. The voltage drop across the resistor is introduced into a hysteresis comparator composed of an operational amplifier CA3140 and four resistors. Then, after passing through a clamping circuit composed of two diodes at its output terminal, the high and low levels are locked to 5V and 0V, respectively. Then, it enters a NAND gate CD4093 to shape the output signal, turning it into a standard square wave with a high level of 5V and a low level of 0V. This square wave will then be used as the input signal for the phase-locked loop frequency multiplier circuit. [align=center] Figure 2 Schematic diagram of zero-crossing detection circuit[/align] 2.2 Phase-locked loop frequency multiplier circuit This phase-locked loop frequency multiplier circuit uses a 74HC4046 phase-locked loop chip, a CD4040 accumulator counter, and a low-pass filter. Its circuit connection diagram is shown in Figure 3. [align=center]Figure 3 Schematic diagram of phase-locked loop (PLL) frequency multiplier circuit[/align] After the phase A voltage passes through the zero-signal detection circuit, a 50Hz square wave synchronized with the phase A voltage is obtained. This square wave serves as the input signal for the PLL frequency multiplier circuit and enters pin 14 of the PLL chip 74HC4046. Pin 4 is the output terminal of the voltage-controlled oscillator (VCO) inside the 74HC4046. Its output signal is input to pin 10 of the CD4040 for a 256-fold frequency multiplication. The multiplied signal is output from pin 13 of the binary counter CD4040 and then enters pin 3 of the 74HC4046, which is the comparison signal input terminal. The phase comparator inside the 74HC4046 performs a phase comparison between the two signals and inputs the result from pin 13, the output terminal of phase comparator II. After passing through the... A low-pass filter composed of [variable name] and [signal name] filters out high-frequency noise before entering the internal voltage-controlled oscillator (VCO) of the 74HC4046 as its control signal. From the above process, we can see that this is a closed-loop control system. Through continuous adjustment, the output signal frequency is made 256 times the input signal frequency, and the frequency difference between the input signal and the comparison signal is zero. 3. Experimental Results and Analysis Figure 4 shows the experimental waveform of the zero-crossing detection circuit when the applied signal frequency is a 50Hz sine wave. [align=center] Figure 4 Zero-crossing signal and sine wave[/align] Figure 5 shows the output experimental waveform of the designed phase-locked loop (PLL) frequency multiplier circuit. [align=center] Figure 5 12.82kHz square wave output by the PLL frequency multiplier circuit[/align] The input voltage of the VCO comes from the output of the low-pass filter, so the output frequency will fluctuate to some extent. The output frequency range of this PLL frequency multiplier circuit is 12.77kHz-12.82kHz. Once the frequency output by the phase-locked loop (PLL) frequency multiplier is captured by the DSP, the AD7656 will start sampling the signal. Due to the pulsation of the output frequency, the sine and cosine values ​​at the sampling points may have some error compared to the sine and cosine values ​​stored in the table. To minimize output frequency fluctuations while maintaining the required PLL speed, the cutoff frequency of the low-pass filter should be reduced as much as possible. References: 1. Guo Ziyong. Research and application of active power filter detection and control technology [D], Changsha: Hunan University, 2007. 2. Chen Zhong. Research on practical key technologies of parallel active power filter [D], Hangzhou: Zhejiang University, 2005. 3. Yuan Shiying. Phase-locked frequency doubling design in power measurement [J], Power Supply and Distribution, 2006.5:84-85 4. Du Guangyu, Chen Xiaoqiao, Wan Zhongtian. Application of phase-locked frequency doubling and quasi-synchronous sampling method in harmonic measurement [J], Journal of Wuhan University (Engineering Science), 2001.34(5):39-44 5. Texas Instruments. Datasheet of CD4046 [R], Texas Instruments, July, 2003 6. Fairchild semiconductor. Datasheet of CD4040 [R], Fairchild semiconductor, Mar, 2002 7. Philips Semiconductors. Datasheet of 74HC4046[R], Philips Semiconductors,Nov,1997