Foreword
By using three or more power modules, each individually packaged with a series of 650V IGBT chips in series, to form a three-level circuit topology to replace the traditional 1200V two-level module, high voltage withstand requirements can be achieved. Moreover, when these identical modules are electrically connected, the power devices are installed separately, optimizing thermal management. This not only improves conversion efficiency and system reliability but also reduces costs.
Three-level module packaging features
Integrating multiple chips into a single module involves considerable complexity in terms of structure and chip design. The following diagram illustrates the circuit topology of SilverMicro's latest packaged module, the 650V/300A NPC.
Figure 1. Internal chip layout and fabrication of the 650V/300A three-level NPC circuit topology.
The module internally encapsulates four IGBT chips and four FWD chips, achieving a compact structure similar to the circuit shown in the right figure.
As shown in the figure, DC+ and DC- represent the positive and negative terminals of the DC voltage, with N being the midpoint. The entire circuit is divided into two symmetrical parts by the midpoint. Its operation is as follows: During the positive half-cycle, VT3 is normally open, while VT1 and VT4 conduct alternately. When VT1 is on, current flows through VT1, VT3, and to the load, resulting in an output voltage of DC+. When VT4 is on, the clamping diode conducts, and current flows through VT4, VD2, and to ground, resulting in an output voltage of zero. During the negative half-cycle, VT4 is always on, while VT2 and VT3 conduct alternately, resulting in output voltages of zero and DC-. Throughout the entire process, the output voltage corresponds to three values: DC+, zero, and DC-, hence the name "three-level circuit topology."
Based on the above description of the working process of the three-level circuit topology, we can see that in the three-level circuit topology, the turn-off voltage of each IGBT is 50% of the bus voltage. In this way, under the same bus voltage, the withstand voltage of the IGBT is reduced by half, which not only reduces the cost but also increases the output capacity.
IGBT chips use trench array technology, which features low on-state voltage, fast turn-off, and low tail current. At the same time, the junction temperature of IGBT chips can reach 175℃, which increases the design requirements of the system. It also requires that the junction temperature of the diodes can also reach 175℃.
Comparison with foreign packaging
Figure 2 Comparison with foreign module internal packaging technology
The image above compares the SME three-level 650V/300A NPC package with foreign packages. To improve module reliability and meet system design requirements, most current packages use electrode soldering, where the connection between the power electrodes and the DBC is soldered. However, under long-term use and high/low temperature cycling conditions, this soldering fatigue can cause cracks in the electrode solder joints, ultimately leading to detachment and failure. The SME three-level module eliminates the need for soldering electrode leads and instead uses ultrasonic welding technology, specifically the highly reliable Al-Ni ultrasonic welding technology. This simplifies the process and improves the module's temperature cycling capability. Signal leads are directly bonded to the electrodes using a rational chip layout design and process. Compared to using flying wire bonding, this significantly improves reliability and reduces gate parasitic parameters, optimizing the characteristics of the drive signal in high-frequency systems.
Static output characteristics
The latest Trench technology 650V chip has low on-state voltage characteristics. As shown in Figure 3, under the conditions of VGE=15V, Ic=300A rated current, and Tj=125℃, the VCE(on) of the IGBT chip is 1.6V, and the forward conduction voltage of the diode is VF=1.5V. Compared with the two-level module, under the same current, the module has less loss and the system temperature change is smaller, which greatly improves the efficiency and reliability of the system design.
Figure 3. Forward output characteristics of GTR300TL65T2SIGBT and FWD
The static conduction characteristics determine the losses of the device in the turn-on state. According to Pon=VCE(on)×Ic, the smaller VCE(on) is, the smaller the loss is. The conduction voltage value provides a design standard for system overcurrent protection.
Switching characteristics
Most 650V chips share the same characteristics as 600V chips, exhibiting high di/dt and dv/dt during switching. However, for most high-efficiency power supply systems, designers aim for rapid turn-off and minimal tail current, which undoubtedly increases the complexity of system design. The GTR300TL65S chip optimizes these switching characteristics. Figure 3 shows the turn-on characteristic waveform of the module tested using a dual-pulse circuit.
Figure 4: GTR300TL65T2S Activation Characteristics Figure 5: Activation Characteristics of Foreign Modules
Vcc=300V,Ic=300A,Rg=10Ω,Tj=125℃ Vcc=300V,Ic=300A,Rg=10Ω,Tj=125℃
Red: Voltage VCE; Blue: Current Ic
From the perspective of turn-on characteristics, the selection of anti-parallel diodes has a significant impact on turn-on characteristics. The faster the diode recovery speed, the higher the di/dt, and the larger the voltage oscillation will be. As shown in the figure above, the GT300TL65T2S diode has a smaller recovery package current and a softer current recovery characteristic in the turn-on state, resulting in smaller waveform oscillation in the turn-on state.
Devices with a withstand voltage of 600V and 650V are typically used in power supply systems, requiring faster turn-off characteristics. However, fast current turn-off time results in a high di/dt. Due to the presence of parasitic inductance, it can be concluded that the higher the di/dt, the higher the reverse turn-off voltage of the system, and the more dangerous the device becomes. Therefore, reducing the inductance of the system and designing a reasonable absorption circuit become the key points and challenges of the design work.
In terms of packaging technology, the module also requires reducing the internal parasitic inductance. A reasonable chip layout, which makes the current path between the chip leads and electrodes shorter and more compact, is better. The following figure shows the typical switching characteristics of a three-level module.
Figure 6: GTR300TL65T2S shutdown characteristics Figure 7: Foreign module power-on characteristics
Vcc=300V,Ic=300A,Rg=10Ω,Tj=125℃ Vcc=300V,Ic=300A,Rg=10Ω,Tj=125℃
Red: Voltage VCE; Blue: Current Ic
The image above compares the turn-off characteristics of the GTR300TL65T2S with those of foreign modules under the same conditions. From the waveform, it can be seen that most manufacturers of 650V chips have very fast current turn-off speeds, with tail currents that are almost zero. This is basically a common feature of chip technology from manufacturers in the current market. In high-frequency systems, the faster the turn-off characteristics of the chip, the lower the dead time setting can be, thereby improving the linearity of the inverter output.
Chip layout thermal simulation calculation
The development of numerical computing technology has facilitated the development of semiconductor products and greatly shortened their design cycle. The temperature field of the T2S module was calculated using finite element analysis software, verifying the rationality of the module's multi-chip layout.
First, based on the module structure, a certain simplification was made. According to the symmetry of the module, half of it was used to build a 1/2 model. Since the thermal conductivity of silicone is very small, it was not modeled in the calculation, and the surface covered by silicone was used as the thermal boundary condition. The 3D model and mesh of the module are shown in Figure (8).
Figure 8. T2S module model and mesh generation
Then, based on the module's workload, the loads and boundary conditions for the finite element analysis were determined. The chip's heat generation was treated as an internal heat source, and the copper base plate was used as a constant-temperature boundary condition with a temperature of 25℃. The calculated temperature cloud map is shown in Figure (9).
Figure 9 Module temperature distribution
The module temperature distribution map shows that the IGBT and diode temperatures are higher than the surrounding areas, with the highest junction temperature located at the center of the IGBT chip at 84.6℃. Due to limited module space, although unavoidable thermal coupling exists between chips, the reasonable chip layout ensures that the overall module thermal design meets operational requirements.
in conclusion
This three-level NPC circuit topology, which integrates multiple 650V chips into a single package module, is used in high-frequency power systems such as UPS and PV. Compared with two-level modules, it reduces device switching losses, optimizes filtering, and improves output current quality. Utilizing optimized chip layout, low-inductance design, and ultrasonic electrode welding packaging technologies enhances device reliability, providing a highly advantageous approach for system design.
