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Design of anti-jitter frequency doubling circuit for incremental photoelectric encoder

2026-04-06 04:30:33 · · #1

In certain industrial automation control fields and equipment applications, there are frequent situations requiring length measurement, and photoelectric encoders are commonly used. Based on their scaling method and signal output format, photoelectric encoders can be divided into three types: incremental, absolute, and hybrid. It is a sensor integrating optics, mechanics, and electronics, possessing significant advantages such as high accuracy, fast response, and stable and reliable performance. It can accurately detect parameters such as angle, rotational speed, and displacement. It can convert physical quantities such as displacement into digital pulse signals, and by calculating the number of pulses, achieve accurate displacement measurement. However, due to factors such as the working environment, incremental photoelectric encoders contain a large number of jitter error pulses in their output signal, which can cause false counting. This paper analyzes the causes of error pulses and designs an effective filtering circuit.

1. Working principle of incremental encoder

An incremental encoder is a sensor that converts the mechanical geometric displacement on the output shaft into pulses or digital signals through photoelectric conversion. It consists of a grating disk and a photoelectric detection device. The grating disk has several rectangular holes evenly spaced on a circular plate of a certain diameter, as shown in Figure 1. Since the photoelectric code disk is coaxial with the motor, the grating disk rotates at the same speed as the motor. The detection device, composed of light-emitting diodes and other electronic components, detects and outputs several pulse signals. The encoder disk has two identical black gratings painted 90° apart, referred to as track A and track B. Their output pulses are also 90° apart. When the encoder rotates forward, track A leads track B by 90°; when the encoder rotates in reverse, track A lags track B by 90°. The output waveform of the encoder under normal conditions is shown in Figure 1.

2. Causes of Bit Error Pulse Generation and Filtering Methods

2.1 Causes of Bit Error Pulse Generation

To illustrate the existence of error pulses, a partial magnification of the encoder code disk is shown. Point 0 in Figure 1 is the center of the encoder's rotating shaft, and the rounded rectangle represents the light-transmitting slits in columns A and B of the code disk. Assuming one phase signal of the encoder is in a certain state, while the other phase signal is at the boundary between high and low level transitions, the error pulses of the encoder are shown in Figures 2(a) and 2(b). Due to the rotation of the motor or the vibration of the mechanical equipment, the encoder output pulses will jitter, thus causing miscounting. This manifests in two ways: firstly, jitter near the light-transmitting window, causing interference pulses, as shown in Figure 2(a) which shows the timing waveform of the A-phase pulse signal jittering at the rising and falling edges, and Figure 2(b) which shows the timing waveform of the B-phase pulse signal jittering at the rising and falling edges; secondly, vibration around a certain point on the encoder, causing interference pulses, as shown in Figures 2(c) and 2(d) which show the timing waveform of the signal jittering around point b on the encoder. The encoder rotates clockwise from point a to point b, then reverses to point a, and then rotates clockwise to point b again. The number of pulses between the two points b is the interference pulse.

2.2 Filtering of Error Pulses

2.2.1 Principle of Filtering Encoder Jitter

Frequency doubling technology is used to filter out jitter pulses. Frequency doubling technology involves counting the rising and falling edges of each pulse in phase A or phase B separately. The normal output waveform of the photoelectric encoder after frequency doubling is shown in Figure 3. When the phase A pulse changes from 0 to 1, if phase B is 0, the encoder rotates forward; if B is 1, the encoder rotates in reverse. When the phase A pulse changes from 1 to 0, if phase B is 1, the encoder rotates forward; if B is 0, the encoder rotates in reverse. During normal encoder output, phases A and B alternate. If phase A changes but phase B does not change, and then phase A changes, this is considered an interference pulse; conversely, the opposite is also considered an interference pulse.

Analyzing Figure 4, the transition edges of phase A are counted at twice the frequency. The high and low levels of phase B are used to determine the forward and reverse rotation of the encoder. The jitter pulses at the edge of phase B have no effect on the frequency doubling count, as shown in Figure 4(b). Analyzing Figure 4(a), the jitter at the edge of phase A is considered to be interference pulses and is filtered out. The positions marked a and b in Figures 4(c) and 4(d) are the physical addresses of the encoder. As shown in Figure 4(d), a and b indicate that the encoder vibrates repeatedly at this location. The transition edges marked (1) and (2) in Figures 4(c) and 4(d) are considered jitter pulses and should be filtered out. The difference between the number of forward and reverse pulse data of phase A is the actual frequency doubling pulse data of phase A.

2.2.2 FPGA Filtering of Encoder Jitter and Simulation Results

Based on the above analysis, this paper uses FPGA to filter out jitter pulses from the output of an incremental photoelectric encoder. The compilation environment is Quartus II 8.0. The logic modules are designed using a combination of graphics and programming languages ​​within the FPGA. The internal logic sub-modules are implemented using Verilog. The structure diagram of the top-level module is shown in Figure 5. The A and B input pins are connected to the A-phase and B-phase signals of the incremental encoder. The Account is a 16-bit data register that outputs the current encoder position. The top-level design includes two modules: BlockA, which filters out jitter pulses from the encoder's A-phase based on the B-phase transition edge record; and BlockA, which records the number of filtered A-phase pulses. The main Verilog program is as follows:

The other module, BlockB, primarily filters out jitter pulses from the encoder's B phase. Based on the principle of encoder jitter filtering, the ENA pin is the output pin of the BlockA module. When there is a transition on the A phase input pin, ENA is 1; when there are consecutive transitions on the A phase pin or a subsequent transition on the B phase, ENA is 0. ENB is the encoder B phase transition enable pin. When ENA is 1, if there is a transition on the B phase, ENB is 1; when ENA is 1, if there are consecutive transitions on the B phase, ENB is 0. The main program is as follows:

Taking the encoder jitter output simulation in Figure 4(a) as an example, the simulation effect is shown in Figure 6. Analysis of the figure shows that phase A outputs 7 pulses, but should actually output 3 pulses. After doubling the frequency, it becomes 14 pulses, but should actually output 6 pulses. After filtering, the pulse counter count is 6. The jitter pulses of phase A are effectively filtered out.

3. Conclusion

Field testing results demonstrate that the algorithm can eliminate interference and jitter in industrial environments and accurately record pulse data. While software filtering could be used, it requires numerous pins and uses two interrupt pins to respond to the rising and falling edges of phase A, wasting CPU resources. Implementing encoder filtering using an FPGA offers greater design convenience and flexibility.

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