Currently, servo motors in domestic CNC machine tools are generally equipped with incremental encoders. However, incremental encoders have relatively low accuracy and output parallel signals. To improve their accuracy, it is necessary to increase the design difficulty of the encoder and increase the output of parallel signals. This is not conducive to long-distance communication between the servo unit and the encoder. In contrast, absolute encoders are used. In addition to having several times higher accuracy than incremental encoders, their signal input and output use high-speed serial communication, saving communication lines and facilitating long-distance communication. At the other end of the encoder, a CPLD is used to communicate with the absolute encoder at high speed. The CPLD then converts the received encoder information into parallel data and transmits it to the DSP in the servo unit for calculation and control. This paper will give the hardware and software design scheme for high-speed serial communication between the CPLD and the absolute encoder.
Hardware Design
The hardware mainly consists of three modules: power supply, CPLD and its peripheral circuits, and absolute encoder interface circuit.
Power module
The power module consists of a switching power supply circuit and a DC/DC power chip, as shown in Figure 1.
The switching power supply in the diagram converts the 220V AC mains voltage into +5V, +15V, and -15V. It filters out various interferences from the mains, and the transformer within isolates the 220VAC from the output +5V, +15V, and -15V. The internal circuit also uses a TL431 to adjust the conduction pulse width of the switching transistor. Therefore, the switching power supply has good anti-interference, safety, stability, and voltage regulation. The TPS7333 is a DC/DC chip that converts the +5V DC voltage into a stable +3.3V DC voltage to supply the CPLD. The TPS7333 has good conversion efficiency, reliability, and voltage regulation. It can convert to +3.3V within an input voltage range of +3.77V to +10V, preventing the CPLD from burning out due to excessively high input voltage.
CPLD and its peripheral circuit modules
The CPLD and its peripheral circuit modules mainly consist of the CPLD, the CPLD programming and download interface circuit (JTAG interface), the DSP interface circuit, the active crystal oscillator, the level conversion circuit, and the ADM485 and its peripheral circuit (the interface circuit responsible for communication with the encoder ) (Figure 2).
This design uses Altera's EPM570T144C5 CPLD, a MAXII chip from Altera. MAXII offers lower cost and power consumption compared to MAXI, while having a higher macrocell count and a latency within 6ns, resulting in high cost-effectiveness. The EPM570T144C5 has 570 macrocells and 144 pins, of which 116 are usable I/O ports, providing sufficient resources. The CPLD primarily handles high-speed serial communication with the absolute encoder and, controlled by the DSP, transmits received encoder data and other information to the DSP in parallel.
The JTAG interface is mainly used to download executable files to the CPLD. Install Altera's Quartus II development environment on the PC, and compile the written VHDL program in this development environment. After ensuring that the compilation is error-free and the function is implemented, connect the download cable to the JTAG interface, and use the programming download tool provided by Quartus II to download to the CPLD circuit board.
The DSP interface consists of 8 data lines, 3 address lines, and 1 control line. The 8 data lines are responsible for transmitting encoder data and other information, the 3 address lines are responsible for transmitting DSP commands, which are decoded at the CPLD terminal. The CPLD transmits encoder data or other information to the DSP through the 8 data lines based on the decoded commands. The control line is mainly used to complete the synchronization control between the CPLD and the DSP.
The 20MHz active crystal oscillator is mainly used to provide a reference clock for the CPLD. Driven by the clock signal, it enables the CPLD to generate a baud rate of 2.5Mb/s to communicate with the encoder and to generate a 10MHz clock for some logic control signals. This crystal oscillator provides a clock frequency of 20MHz and requires a power supply of 3.3V DC voltage.
The level conversion circuit is mainly responsible for converting 3.3V voltage to 5V or 5V voltage to 3.3V. This is because the CPLD core and I/O ports require a power supply voltage of 3.3V, while the ADM485 and absolute encoder require a power supply voltage and I/O port drive circuit of 5V. Therefore, the level conversion chip LVC4245A is needed to convert 3.3V to 5V or 5V to 3.3V.
The ADM485 and its peripheral circuitry form the hardware interface for high-speed communication between the CPLD and the absolute encoder. The ADM485 operates at 5V and has a maximum communication rate of 5Mb/s. Using two ADM485 chips for interfacing improves the anti-interference capability of the communication line, and the longest transmission distance can reach 1.2km. Its peripheral circuit is shown in Figure 3. The right half of the dashed line belongs to the peripheral circuit of the absolute encoder. The pull-up and pull-down resistors are both 1K ohms, and the current limiting resistor is 220 ohms. SDAT of ADM485 is the data output pin, SRQ of ADM485 is the data input pin, and DE of ADM485 is the external control pin, which is controlled by the CPLD. Since the RS-485 communication protocol is half-duplex, ADM485 can only be in the state of sending or receiving data. When DE of ADM485 is high, ADM485 is in the data output state (i.e., CPLD receives data), and when DE of ADM485 is low, ADM485 is in the data input state (i.e., CPLD sends data).
Absolute encoder interface module
The absolute encoder interface module refers to the power supply and signal input/output interface circuit inside the absolute encoder. Its circuit is consistent with the ADM485 and its peripheral circuits mentioned above. It also uses the ADM485 chip and some pull-up, pull-down, and current-limiting resistors, as shown in Figure 3. The left half of the dashed line is the internal interface circuit of the absolute encoder, which is responsible for connecting with the external ADM485 (the right half of the dashed line). The ADM485 is controlled by the control chip inside the encoder. When the encoder receives a command from the CPLD, the control chip makes a judgment and sends out the corresponding data. At the same time, it controls the DE of the ADM485 to be high. Even if the ADM485 is in the transmitting state, after sending the data, the control chip puts the DE of the ADM485 back to the low level to facilitate receiving commands from the CPLD at any time.
Software Design
The software refers to the VHDL program of the CPLD, which mainly consists of six software sub-modules: frequency divider, receiving DSP control commands, CPLD logic control, baud rate generator, receiving and transmitting data, and serial-to-parallel conversion and data transmission (Figure 4).
Frequency divider module
The frequency divider module mainly divides the 20MHz input clock frequency into 10MHz and 2.5MHz clock frequencies. The 10MHz clock is mainly used to power the CPLD logic control module, while the 2.5MHz clock is mainly used to power the baud rate generator module.
DSP control command receiving module
The DSP control command receiving module actually acquires the control signals sent by the DSP in real time and decodes the control signals in a timely manner. After the decoding is completed, it immediately forwards them to the CPLD logic control module.
CPLD logic control module
The CPLD logic control module is the core of the entire CPLD software. After receiving the decoded data, it immediately performs logic control operations and quickly controls the receiving and transmitting data modules and the serial conversion and transmitting data modules.
Baud rate generator module
The baud rate generator module mainly provides a 2.5Mb/s baud rate for the receiving and transmitting data modules.
Data receiving and sending module
The receiving and transmitting data module is an important component of the entire CPLD software. It is mainly responsible for high-speed communication with the absolute encoder. Since its communication method is asynchronous serial communication, its baud rate, communication data format and RS-485 communication protocol must be the same as those of the absolute encoder.
Serial-to-parallel conversion and data transmission module
The serial-to-parallel conversion and data transmission module mainly converts the received encoder serial data into parallel data and latches the data in the CPLD latch. When the CPLD logic control module controls its data transmission, the data latched in the CPLD latch is released to the DSP in parallel for the DSP to perform calculations and control.
Conclusion
This design has completed the hardware and software design. It only takes 31μs to read any position data of the motor rotor with an absolute encoder , and the communication rate can reach 2.5Mb/s. When this design is integrated into the servo drive unit, the motor speed can be driven and controlled up to 6000 rpm, and the position accuracy of the motor rotor can be controlled at the μM level.
