Figure 1. Typical analog signal chain of a receiver with downconversion stage
Integrating DDC functionality into the RF ADC eliminates the need for an additional analog downconversion stage and allows the spectrum in the RF frequency domain to be directly downconverted to baseband for processing. The RF ADC's ability to process the spectrum in the GHz frequency domain relaxes the requirements for multiple downconversions in the analog domain. This DDC functionality preserves the spectrum while allowing filtering via decimation filtering, which also provides the advantage of improved in-band dynamic range (increased SNR). A more detailed discussion of this topic can be found in: "Grandfather-era ADCs are a thing of the past , " and "Gigabit Sampling ADCs Ensure Direct RF Conversion . " These articles further discuss the AD9680 and AD9625, and their DDC functionality.
Figure 2. Receiver signal chain using RFADC (integrated DDC)
This article focuses primarily on the DDC (Distributed Damping Control) functionality in the AD9680 (as well as the AD9690 , AD9691, and AD9684). To understand the DDC function and how to analyze the output spectrum when DDC is integrated into an ADC, we will use the AD9680-500 as an example. The folding tool from the ADI website will be used as a supplementary tool. This simple yet powerful tool can help understand aliasing effects in ADCs, which is the first step in analyzing the output spectrum of RF ADCs with integrated DDC, such as the AD9680.
In this example, the AD9680-500 operates with an input clock of 368.64MHz and an analog input frequency of 270MHz. First, it's important to understand the settings of the digital processing module in the AD9680. The AD9680 will be configured to use a digital downconverter (DDC) with real inputs and complex outputs. The numerically controlled oscillator (NCO) tuning frequency is set to 98MHz, half-band filter 1 (HB1) is enabled, and 6dB gain is enabled. Since the output is complex, the complex-to-real conversion module is disabled. The basic schematic of the DDC is shown below. The following is important for understanding how the input signal tone is processed: the signal first passes through the NCO, causing a frequency shift in the input signal tone; then it passes through the decimation module, and optionally through the gain module, and then optionally through the complex-to-real conversion module.
Figure 3. DDC signal processing module in AD9680
It's also important to understand the signal flow through the AD9680 from a macroscopic perspective. The signal enters the analog input, passes through the ADC core, enters the DDC, passes through the JESD204B serializer, and is then output through the JESD204B serial output channel. See the AD9680 functional block diagram in Figure 4.
Figure 4. AD9680 Functional Block Diagram
With an input sampling clock of 368.64 MHz and an analog input frequency of 270 MHz, the input signal will alias into the first Nyquist region at 98.64 MHz . The second harmonic of the input frequency will alias into the first Nyquist region at 171.36 MHz, while the third harmonic will alias to 72.72 MHz. This can be seen from the frequency folding tool curves in Figure 5.
Figure 5. ADC output spectrum in the frequency folding tool
The frequency folding tool curve shown in Figure 5 illustrates the signal state at the ADC core output before the signal passes through the DDC in the AD9680. The first processing module in the AD9680 is the NCO, which shifts the spectrum 98MHz to the left in the frequency domain (remember the tuning frequency is 98MHz). This shifts the analog input down from 98.64MHz to 0.64MHz , the second harmonic down to 73.36MHz , and the third harmonic down to –25.28MHz (remember we are observing the complex output). This can be seen in the VisualAnalog FFT curve, as shown in Figure 6 below.
Figure 6. Complex FFT output after DDC (NCO=98MHz, 2x decimation)
The FFT curves in Figure 6 clearly show how the NCO shifts the frequencies we observed in the frequency folding tool. Interestingly, we can see an unexpressed tone in the FFT. However, is this tone truly unexpressed? The NCO doesn't shift all frequencies. In this example, it shifts the aliased 98MHz fundamental input tone down to 0.64MHz , the second harmonic to 73.36MHz , and the third harmonic to -25.28MHz . Furthermore, another tone is also shifted, appearing at 86.32MHz . Where does this tone originate? Is it due to signal processing by the DDC or ADC? The answer is: yes and no.
Let's look at this scenario in more detail. The frequency folding tool does not account for the DC offset of the ADC. This DC offset causes a tone at DC (or 0Hz). The frequency folding tool assumes that the ADC is an ideal device with no DC offset. In the actual output of the AD9680, the DC offset tone at 0Hz is shifted down to -98MHz. Due to complex mixing and decimation, the DC offset tone folds back to the first Nyquist zone in the real frequency domain. For a complex input signal whose tone shifts into the second Nyquist zone, it will wrap back to the first Nyquist zone in the real frequency domain. Since decimation is enabled and the decimation rate is equal to 2, our decimated Nyquist zone width is 92.16MHz (recall: fs = 368.64MHz , decimation sampling rate is 184.32MHz , Nyquist zone is 92.16MHz ). The DC offset signal tone shifts to -98MHz, which is 5.84MHz outside the 92.16MHz Nyquist zone boundary. When this tone wraps back to the first Nyquist zone, its offset is the same as the Nyquist zone boundary in the real frequency domain, i.e., 92.16MHz - 5.84MHz = 86.32MHz . This is exactly the tone we saw in the FFT curve above! Therefore, technically, the ADC generates the signal (because it is DC offset), while the DDC slightly shifts it. This is where good frequency planning comes in. Proper frequency planning helps avoid this situation.
We've now discussed an example using an NCO and an HB1 filter with a decimation rate of 2; let's add something more to this example. We'll increase the DDC decimation rate to observe the frequency folding effect and the transitions when using a higher decimation rate and NCO frequency tuning.
In this example, we observe the operation of the AD9680-500 with a 491.52MHz input clock and a 150.1MHz analog input frequency. The AD9680 is configured to use a digital downconverter (DDC) with real input, complex output, NCO tuning frequency of 155MHz, half-band filter 1 (HB1) and half-band filter 2 (HB2) enabled (total decimation rate equal to 4), and 6dB gain enabled. Since the output is complex, the complex-to-real module is disabled. Recall the basic schematic of the DDC in Figure 3, which illustrates the signal flow through the DDC. Similarly, the signal first passes through the NCO, offsetting the frequency of the input signal tone, and then through the decimation and gain modules, and in this example, bypassing the complex-to-real module.
We will again use the frequency folding tool to help understand the aliasing effect of the ADC in order to assess the location of the analog input frequency and harmonics in the frequency domain. In this example, we have a real signal with a sampling rate of 491.52 MSPS, a decimation rate of 4, and a complex output. The signal displayed at the ADC output using the frequency folding tool is shown in Figure 7.
Figure 7. ADC output spectrum in the frequency folding tool
With an input sampling clock of 491.52MHz and an analog input frequency of 150.1MHz , the input signal will remain in the first Nyquist region. The second harmonic of the input frequency at 300.2MHz will alias into the first Nyquist region at 191.32MHz , while the third harmonic at 450.3MHz will alias into the first Nyquist region at 41.22MHz . This is the signal state at the ADC output before the signal passes through the DDC.
Now, let's look at how the signal passes through the digital processing modules inside the DDC. We'll examine the signal entering each stage and observe how the NCO shifts the signal, and how the decimation process subsequently folds the signal. We'll keep the input sampling rate of the curve ( 491.52 MSPS), with the fs term related to this sampling rate. Let's observe the general process, as shown in Figure 8. The NCO shifts the input signal to the left. Once the signal shifts more than –fs/2 in the complex (negative frequency) domain, it folds back to the first Nyquist zone. Next, the signal passes through the first decimation filter HB1 with a decimation rate of 2. The decimation process is shown in the figure, but the filter response is not shown, although the two operations occur simultaneously. This is for simplicity. After the first 2x decimation, the spectrum from fs/4 to fs/2 is converted to frequencies from –fs/4 to DC. Similarly, the spectrum from –fs/2 to –fs/4 is converted to frequencies from DC to fs/4. The signal now passes through the second decimation filter HB2, which is also 2x decimated (the total decimation is now equal to 4). The spectrum from fs/8 to fs/4 will be converted to frequencies from –fs/8 to DC. Similarly, the spectrum from –fs/4 to –fs/8 will be converted to frequencies from DC to fs/8. Although decimation is shown in the figure, the decimation filtering operation is not shown.
Figure 8. Effect of decimation filter on ADC output spectrum—general example
Recall that in the previous example, we discussed an input sampling rate of 491.52 MSPS and an input frequency of 150.1 MHz . The NCO frequency was 155 MHz, and the decimation rate was 4 (the actual NCO frequency was 154.94 MHz due to the NCO resolution). Therefore, the output sampling rate was 122.88 MSPS. Since the AD9680 is configured for complex mixing, we need to include the complex frequency domain in our analysis. Figure 9 shows that the frequency conversion is very busy, but the signal flow can be seen if you look closely.
Figure 9. The effect of the decimation filter on the ADC output spectrum—a practical example
Spectrum after NCO shift:
1. The base frequency was shifted from + 150.1MHz to -4.94MHz .
2. The baseband image shifts from -150.1MHz and wraps back to 186.48MHz .
3. The second harmonic frequency shifted from 191.32MHz to 36.38MHz .
4. The third harmonic shifted from + 41.22MHz to -113.72MHz .
Spectrum after 2x extraction:
1. The base frequency remains at -4.94MHz .
2. The baseband image is down-converted to -59.28MHz and attenuated by the HB1 decimation filter.
3. The second harmonic frequency remains at 36.38 MHz.
4. The third harmonic is significantly attenuated by the HB1 decimation filter.
Spectrum after 4x extraction:
1. The base frequency remains at -4.94MHz .
2. The baseband image remains at -59.28MHz .
3. The second harmonic frequency remains at -36.38 MHz.
4. The third harmonic is filtered and almost completely eliminated by the HB2 decimation filter. (Figure 9 )
Now, let's look at the actual measurements of the AD9680-500. We can see the fundamental frequency is at -4.94MHz . The fundamental image is at -59.28MHz with an amplitude of -67.112dBFS , meaning the image attenuation is approximately 66dB. The second harmonic is at 36.38MHz . Note that VisualAnalog cannot correctly find the harmonic frequencies because it does not resolve the NCO frequency and decimation rate.
Figure 10. FFT complex output curve of the signal after passing through DDC (NCO=155MHz, 4x decimation)
If the DDC is set to real input and complex output, and the NCO frequency is 155MHz (actually 154.94MHz ), then the output spectrum of the AD9680-500 can be seen from the FFT, with a decimation rate of 4. I encourage everyone to study the signal flow diagram to understand how the spectrum shifts and transforms. I also encourage everyone to study the examples in this article in detail to understand the impact of the DDC on the ADC output spectrum. I suggest printing Figure 8 and referring to it at any time when analyzing the output spectra of the AD9680, AD9690, AD9691, and AD9684. When working with these products, I encountered many frequency issues related to the ADC output spectrum that people thought were inexplicable. However, once the analysis was completed and the signal flow was analyzed through the NCO and decimation filter, the previously inexplicable spectral spurious signals proved to be signals that were actually present. I hope that by reading and learning from this article, you will be more prepared to deal with problems the next time you encounter an ADC with an integrated DDC. Stay tuned for Part 2—we will continue to discuss the DDC from other aspects and how to simulate its behavior. We will discuss the decimation filter response caused by ADC aliasing, provide more examples, and use VirtualEval to observe the operation of the DDC in the AD9680 and its impact on the ADC output spectrum.
