In Part 1, "The Development and Updating of Digital Down -Converters – Part 1," we discussed the industry trend of frequency sampling in higher RF bands and how digital down-converters (DDCs) support such radio architectures. Several technical aspects of the DDC included in the AD9680 series were explored. One aspect is that the higher input sampling bandwidth allows radio architectures to sample directly at higher RF frequencies and convert the input signal directly to baseband. The DDC enables the RF sampling ADC to digitize such signals without handling large data throughput. Tuning and decimation filtering mechanisms in the DDC can be used to adjust the input band and filter out interfering frequencies.
In Part 1, we analyzed an example using the NCO and decimation filtering in a DDC to observe the effects of frequency folding and conversion in the DDC. Now we further analyze decimation filtering and how ADC aliasing affects the effective response of the decimation filter. Again, we will use the AD9680 as an example. We have normalized the decimation filter response for easier viewing and understanding, and for applicability to each speed level. The decimation filter response is proportional only to the sampling rate. The filter response plots in this paper do not provide an exact, concrete relationship between insertion loss and frequency, but rather visually depict an approximate response of the filter. These examples provide a better understanding of the decimation filter response, giving a general idea of where the filter's passband and stopband lie.
As mentioned earlier, the AD9680 features four DDCs, each containing an NCO, up to four cascaded half-band (HB) filters (also known as decimation filters), an optional 6dB gain module, and an optional complex-to-real converter module, as shown in Figure 1. As discussed in Part 1, the signal first passes through the NCO, causing a frequency shift in the input signal tone, and then passes through the decimation module, optionally the gain module, and optionally the complex-to-real converter module.
Figure 1. DDC signal processing module in AD9680
First, we will discuss the DDC decimation filter when the complex-to-real module is enabled in the AD9680. This means the DDC will be configured to accept real inputs and produce real outputs. In the AD9680, the complex-to-real module automatically shifts the input frequency upwards by fS/4. Figure 2 shows the low-pass response of the HB1 filter. This is the HB1 response, showing the real and complex domain responses. To understand how the filter actually works, we must first observe the filter's fundamental responses in the real and complex domains, thus observing the low-pass response. The HB1 filter has a passband that occupies 38.5 % of the real Nyquist region. It also has a stopband that occupies 38.5 % of the real Nyquist region, with its transition band occupying the remaining 23%. Similarly, in the complex domain, the passband and stopband each occupy 38.5 % of the complex Nyquist region (77% total), while the transition band occupies the remaining 23%. As shown in Figure 2, the filter is a mirror image between the real and complex domains.
Figure 2. HB1 filter response—real and complex domain responses
Now we can observe what happens when the DDC is set to real mode by enabling the complex-to-real converter. Enabling the complex-to-real converter results in an fS/4 shift in the frequency domain. As shown in Figure 3, the frequency shift and the resulting filter response can be seen. Note the solid and dashed lines of this filter response. The solid line and the shaded area represent the new filter response after the fS/4 frequency shift (the resulting filter response cannot cross the Nyquist boundary). The dashed line shows the filter response that would have existed if it had not crossed the Nyquist boundary.
Figure 3. HB1 filter response—DDC real mode (complex to real converter enabled)
Note that in Figures 2 and 3, the bandwidth of the HB1 filter remains constant. The difference between the two is the fS/4 frequency shift and the center frequency within the first Nyquist zone. However, it should be noted that in Figure 2, we use 38.5 % of the Nyquist zone for the real part of the signal and another 38.5 % for the complex part. In Figure 3, the complex-to-real module is enabled, and 77% of the Nyquist zone is used for the real signal, while the complex domain has been discarded. Except for the fS/4 frequency shift, the filter response remains unchanged. It should also be noted that one consequence of this conversion is that the decimation rate is now equal to 1. The effective sampling rate remains fS, but only 77% of the bandwidth within the Nyquist zone is available, instead of the entire Nyquist zone. This means that when the HB1 filter and the complex-to-real module are enabled, the decimation rate is equal to 1 (see the AD9680 datasheet for more information).
Next, we'll examine the filter's response at different decimation rates (i.e., enabling multiple half-band filters) and how ADC input frequency aliasing affects the effective decimation filter response. The solid blue line in Figure 4 represents the actual frequency response of HB1. The dashed line represents the effective aliasing response of HB1 due to ADC aliasing. Since the input frequencies of the second, third, fourth… Nyquist zones are actually aliased into the first Nyquist zone of the ADC, the HB1 filter response is effectively aliased into these Nyquist zones. For example, a signal residing at 3 fS/4 will alias into fS/4 of the first Nyquist zone. It's crucial to understand that the HB1 filter response only resides in the first Nyquist zone, and it's ADC aliasing that causes the effective HB1 response to appear as if it's aliased into other Nyquist zones.
Figure 4. HB1 effective filter response caused by ADC aliasing
Now let's discuss the case where HB1+HB2 is enabled. This results in a decimation rate of 2. The solid blue line here also represents the actual frequency response of the HB1+HB2 filter. The center frequency of the filter passband remains fs/4. Enabling HB1+HB2 will result in a usable bandwidth of 38.5 % of the Nyquist zone. Again, note the aliasing effect of the ADC and its impact on the HB1+HB2 filter combination. A signal appearing at 7 fs/8 will alias to fs/8 of the first Nyquist zone. Similarly, a signal appearing at 5 fs/8 will alias to 3 fs/8 of the first Nyquist zone. These examples of enabling complex-to-real converter modules can be easily extended from containing HB1+HB2 to containing either or both of the HB3 and HB4 filters. Note that when the DDC is enabled, the HB1 filter is not bypassed, while the HB2, HB3, and HB4 filters are selectively enabled.
Figure 5. Effective filter response of HB1+HB2 due to ADC aliasing (decimation rate = 2)
We have already discussed the real-valued operating mode of the decimation filter when enabled; now we can explore the complex-valued operating mode of the DDC. Let's continue with the AD9680 as an example. Similar to the real-valued operating mode of the DDC, we will show the normalized decimation filter response here. Again, the example filter response plot does not show the exact relationship between insertion loss and frequency, but rather depicts the approximate response of the filter visually. This is done to facilitate a better understanding of how ADC aliasing affects the filter response.
When using DDC in complex mode, it is configured to have a complex output consisting of real and complex frequency domains (commonly referred to as I and Q). Referring back to Figure 2, the HB1 filter has a low-pass response, with a passband that accounts for 38.5 % of the real Nyquist region. It also has a stopband that accounts for 38.5 % of the real Nyquist region, and a transition band that accounts for the remaining 23%. Similarly, in the complex domain, the passband and stopband each account for 38.5 % of the complex Nyquist region (77% total), while the transition band accounts for the remaining 23%.
When the HB1 filter is enabled, the DDC operates in complex output mode with a decimation rate of two, and the output sampling rate is half the input sampling clock. Extending the curves in Figure 2 illustrates the effect of ADC aliasing as shown in Figure 6. The solid blue line represents the actual filter response, while the dashed blue line represents the effective aliasing response of the filter due to ADC aliasing. A 7fS/8 input signal will alias to fS/8 in the first Nyquist zone, placing it within the passband of the HB1 filter. The complex mirror image of the same signal resides at –7fS/8 and will alias to –fS/8 in the complex domain, placing it within the passband of the HB1 filter in the complex domain.
Figure 6. HB1 effective filter response due to ADC aliasing (decimation rate = 2) – complex number
Next, we will discuss the case where HB1+HB2 is enabled, as shown in Figure 7. This results in a decimation rate of 4 for each I and Q output. The blue solid line here also represents the actual frequency response of the HB1+HB2 filter. Enabling both HB1 and HB2 filters simultaneously will result in an available bandwidth of 38.5 % of the decimated Nyquist zone in both the real and complex domains ( 38.5 % of fS/4, where fS is the input sampling clock). Note the aliasing effect of the ADC and its impact on the HB1+HB2 filter combination. A signal appearing at 15fS/16 will alias to fS/16 of the first Nyquist zone. The signal has a complex mirror image at –15fS/16 in the complex domain and will alias to –fS/16 of the first Nyquist zone in the complex domain. Similarly, these examples can be extended to the case where both HB3 and HB4 are enabled. These are not shown in this paper, but can be easily deduced from the HB1+HB2 response shown in Figure 7.
Figure 7. Effective filter response of HB1+HB2 due to ADC aliasing (decimation rate = 4) — complex number
Looking at all these decimation filter responses, you might be wondering, "Why are we decimating?" and "What are the benefits?" Different applications have different requirements, and these requirements can benefit from decimating the ADC output data. One reason is to increase the signal-to-noise ratio over a narrow band in the RF band. Another reason is to reduce the processing bandwidth, which allows for a lower output channel rate on the JESD204B interface, facilitating the use of a low-cost FPGA. By using all four decimation filters, the DDC achieves processing gain and improves SNR by up to 10dB. In Table 1, we can see the available bandwidth, decimation rate, output sampling rate, and ideal SNR improvement provided by different decimation filter choices when the DDC operates in real and complex modes.
Table 1. Characteristics of DDC Filter (AD9680)
The discussion of DDC operating modes helps to gain a deeper understanding of the real and complex operating modes of the decimation filter in the AD9680. Using decimation filtering offers several advantages. DDC can operate in either real or complex mode, allowing users to employ different receiver topologies depending on the specific application requirements. Combined with the content described in Part I, this also helps to explore a real-world example using the AD9680. This example will integrate measured data and simulation data derived from VirtualEval to facilitate comparison of results.
In this example, we will use the same conditions as in Part 1. The input sampling rate is 491.52 MSPS, and the input frequency is 150.1 MHz . The NCO frequency is 155 MHz, and the decimation rate is set to 4 (the actual NCO frequency is 154.94 MHz due to the NCO resolution). Therefore, the output sampling rate is 122.88 MSPS. Since the DDC performs complex mixing, the analysis includes the complex frequency domain. Note that the response of the decimation filter has been added to Figure 8, represented by the dark purple curve.
Figure 8. Signal passing through the DDC signal processing module—decimation filtering
Spectrum after NCO shift:
1. The base frequency was shifted from + 150.1MHz to -4.94MHz .
2. The baseband image shifts from -150.1MHz and wraps back to + 186.48MHz .
3. The second harmonic frequency shifted from 191.32MHz to 36.38MHz .
4. The third harmonic shifted from + 41.22MHz to -113.72MHz .
Spectrum after 2x extraction:
1. The base frequency is -4.94MHz .
2. The baseband image is down-converted to -59.28MHz and attenuated by the HB1 decimation filter.
3. The second harmonic is located at 36.38MHz .
4. The third harmonic is attenuated by the HB1 decimation filter.
Spectrum after 4x extraction:
1. The base frequency is -4.94MHz .
2. The baseband image is located at -59.28MHz and is attenuated by the HB2 decimation filter.
3. The second harmonic is located at -36.38MHz and is attenuated by the HB2 decimation filter.
4. The third harmonic is basically completely eliminated by the HB2 decimation filter after filtering.
The measured results of the AD9680-500 are shown in Figure 9. The fundamental frequency is located at -4.94MHz . The fundamental frequency image is located at -59.28MHz with an amplitude of -67.112dBFS , meaning the image attenuation is approximately 66dB. The second harmonic is located at 36.38MHz and attenuated by approximately 10 to 15dB. The third harmonic, after sufficient filtering, does not exceed the noise floor in the measured results.
Figure 9. FFT complex output of the signal after passing through DDC (NCO=155MHz, 4x decimation)
VirtualEval can now be used to compare simulation results with measured results. First, open the tool from the website and select the ADC to be simulated (see Figure 10). The VirtualEval tool is located under VirtualEval on the ADI website. The AD9680 model in VirtualEval includes a newly developed feature that allows users to simulate different ADC speed levels. This feature is important because this example uses the AD9680-500. After VirtualEval loads, you will first be prompted to select a product category and product. Note that VirtualEval covers not only high-speed ADCs but also precision ADCs, high-speed DACs, and integrated/dedicated converters.
Figure 10. Product Categories and Selection in VirtualEval
Select AD9680 from the product list. This will open the main page for the AD9680 simulation. The AD9680 model in VirtualEval also includes a block diagram detailing the internal configuration of the ADC's analog and digital functions. This block diagram is identical to the one in the AD9680 datasheet. Select the desired speed level from the drop-down menu on the left side of this page. In this example, a speed level of 500MHz is selected, as shown in Figure 11.
Figure 11. AD9680 speed level selection and block diagram in VirtualEval
Then, in order to perform the FFT simulation, the input conditions must be set (see Figure 12). To recap, the test conditions in this example include a clock rate of 491.52 MHz and an input frequency of 150 MHz. DDC is enabled, the NCO frequency is set to 155 MHz, the ADC input is set to Real, the complex-to-real module (C2R) is disabled, the DDC decimation rate is set to Four (4), and the 6 dB gain in DDC is enabled. This means that DDC will be set to have a real input signal and a complex output signal, and the decimation rate is 4. The 6 dB gain in DDC is enabled to compensate for the 6 dB loss caused by the mixing process in DDC. VirtualEval can only display one of the results, either noise or distortion, at a time, so two graphs are listed in the text to show the noise result (Figure 12) and the distortion result (Figure 13), respectively.
Figure 12. AD9680 FFT simulation in VirtualEval—noise results
Figure 13. AD9680 FFT simulation in VirtualEval—distortion results
VirtualEval displays many performance parameters. This tool provides the location of the fundamental frequency image and the locations of each harmonic, which is very convenient for frequency planning. It also allows users to see if the fundamental frequency image or any harmonic tones appear within the desired output spectrum, making frequency planning easier. VirtualEval simulation yields an SNR of 71.953 dBFS and an SFDR of 69.165 dBc. However, it should be considered that the fundamental frequency image typically does not appear in the output spectrum; if we eliminate spurious signals, the SFDR becomes 89.978 dB (or 88.978 dBc if the reference input power is –1 dBFS).
Figure 14. AD9680 FFT measurement results
The VirtualEval simulator does not include the fundamental frequency image when calculating SNR. Please be sure to adjust the settings in VisualAnalog® to ignore the fundamental frequency image in the measurement results to obtain the correct SNR. This method is suitable for frequency planning when the fundamental frequency image is not within the desired frequency band. The measured SNR is 71.602 dBFS, very close to the simulation result of 71.953 dBFS in VirtualEval. Similarly, the measured SFDR is 91.831 dBc, very close to the simulation result of 88.978 dBc.
VirtualEval delivers exceptional accuracy in predicting hardware behavior. All you need is a comfortable chair and a cup of hot tea or coffee to predict device behavior. Particularly for ADCs with DDC (such as the AD9680), VirtualEval effectively simulates various ADC performance characteristics (including image and harmonic distortion), facilitating frequency planning and keeping interference signals out of the band as much as possible. With the increasing use of carrier aggregation and direct RF sampling, having tools like VirtualEval in your toolbox will greatly enhance your work. These tools accurately predict ADC performance, helping system designers plan appropriate frequencies for certain applications (such as communication systems, military/aerospace radar systems, and many other types of applications). We recommend taking full advantage of the digital signal processing capabilities of ADI's next-generation ADC devices. We also suggest using VirtualEval to plan your next design and anticipate expected performance.
