The world we live in, made up of always-on PCs, tablets, and smartphones, owes its existence to a remarkable trend: the continuous miniaturization of metal-oxide-semiconductor field-effect transistors (MOSFETs). MOSFETs are the fundamental building blocks of most integrated circuits, and in the past half-century, their size has shrunk to a fraction of their original size, from tens of micrometers in the 1960s to just tens of nanometers today. With each generation of MOSFETs becoming smaller, MOSFET-based chips operate faster and are more energy-efficient than ever before.
This trend has brought about the longest and greatest series of victories in industrial history, giving us devices, capacity, and convenience unimaginable to previous generations. However, this steady progress has been threatened, and the crux of the problem lies in quantum mechanics.
Electrons possess a perplexing ability to penetrate energy barriers—a phenomenon known as quantum tunneling. As chip manufacturers pack more and more transistors onto a chip, and transistors become smaller and smaller, the distance between different transistor regions is compressed. Consequently, electron barriers that were once thick enough to block electric current are now extremely thin, allowing electrons to pass through them very quickly.
Chip manufacturers have stopped thinning a crucial part of transistors—the gate oxide layer. This layer separates the gate, which controls the transistor's on/off state, from the conductive channel via electrons. Thinning this oxide layer allows more charge to flow into the channel, accelerating current flow and making the transistor operate faster. However, the oxide layer thickness cannot be much smaller than 1 nanometer, which is roughly what we can achieve today. Exceeding this limit results in excessive charge flowing within the channel when the transistor is in the "off" state, whereas ideally, there should be no charge flowing. This is just one of several potential leakage points.
For a long time, determining when size reduction will finally end has been a difficult task. Industry roadmaps now predict that MOSFET miniaturization will continue until 2026, when the gate length will be only 5.9 nanometers—about a quarter of its current length. This timeline assumes that we can find better materials to plug leaks. However, even if we find such a material, we will still need to find alternatives to MOSFETs as soon as possible if we hope to continue to improve performance as we are used to.
We cannot prevent electrons from tunneling through this thin barrier, but we can harness this phenomenon for our own use. In recent years, a newer transistor design—the tunneling field-effect transistor (TFET)—has seen rapid development. Unlike MOSFETs, which control current flow by raising or lowering the energy barrier, TFETs maintain a high energy barrier. The device controls turn-on and turn-off by altering the probability of electrons appearing on one side of the barrier on the other.
This working principle differs significantly from that of traditional transistors. However, this may be precisely what we need to vigorously develop now that MOSFETs have reached a point of stagnation. It paves the way for the development of faster, denser, and more energy-efficient circuits to extend Moore's Law into the next decade.
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This wasn't the first time transistors had changed form. Initially, semiconductor-based computers used circuits made of bipolar transistors. But just a few years after the silicon MOSFET was introduced in 1960, engineers realized they could create two complementary switches that could together form a complementary metal-oxide-semiconductor (CMOS) circuit. Unlike bipolar transistors, this circuit consumed energy only when it was on. Since the first CMOS-based integrated circuit appeared in the early 1970s, MOSFETs have dominated the market.
In many ways, MOSFETs are not much different from bipolar transistors. Both control the flow of current by raising or lowering the energy barrier—somewhat like raising or lowering a sluice gate on a river. In this case, the "river water" consists of two types of charge carriers: electrons and holes, the latter being a positively charged entity, essentially an atom in the material lacking an electron in its outer shell.
For these charge carriers, there are two permissible energy ranges, or energy bands. Electrons, which have enough energy to flow freely in a material, reside in the conduction band. Holes, on the other hand, flow in the lower energy band (called the "valence band"), moving from one atom to another, much like how an empty parking lot can become a full one due to nearby cars constantly driving in and out.
These energy bands are fixed, but we can change their associated energies by adding impurities or doping atoms to raise or lower the energies, thereby altering the conductivity of the semiconductor. An n-type semiconductor, doped with extra electrons, conducts negatively charged electrons; a p-type semiconductor, through doping that reduces the number of electrons, conducts positively charged holes.
If we combine these two semiconductor types, we get a misaligned energy band, creating an energy barrier in between. To fabricate a MOSFET, we inject a material between the two complementary types, using an npn or pnp configuration. This creates three regions in the middle of the transistor: the source (where charge enters the component), the channel, and the drain (where charge exits).
The two pn junctions in each transistor provide an electronic energy barrier for charge flow, and the transistor can be turned on by applying a voltage to the gate above the channel. Applying a positive voltage to an n-channel MOSFET causes the channel to attract more electrons because it reduces the energy required for electrons to move into the channel. Applying a negative voltage to a p-channel MOSFET produces the same effect on holes.
This simple method of lowering the energy barrier is the most widely used current control mechanism in semiconductor electronics. Diodes, lasers, bipolar transistors, thyristors, and most field-effect transistors utilize this method. However, this method has a physical limitation: transistors require a certain voltage to be turned on or off. This is because electrons and holes are constantly in motion due to thermal energy, and the most energetic of them overflows the energy barrier. At room temperature, if the energy barrier is reduced by 60 millivolts, the current flowing through the barrier increases tenfold; each decimal change in current requires a 60-mV change.
All this current leakage occurs below the device's threshold voltage. The threshold voltage is the voltage required to turn on the transistor. Device physicists call this region of reduced energy barrier the subthreshold region, and a voltage of 60 millivolts per decimal is considered the minimum subthreshold swing. To maintain low power consumption, the subthreshold swing should be minimized. This reduces the voltage required to turn the device on, and consequently reduces the leakage current when it is turned off.
Subthreshold swing wasn't a major issue in the past because chips required higher voltages to operate. However, it's now starting to interfere with our efforts to reduce power consumption. This is partly because circuit designers want to ensure their logic components have a clear distinction between the currents that define "0" and "1". Transistors are typically designed so that the current they carry when on is 10,000 times the current they leak when off. This means that to turn on a transistor, at least 240 millivolts, or four decimal units of current, needs to be applied, since each decimal requires 60 millivolts.
In practice, CMOS circuits typically operate at much higher voltages, close to 1 volt. This is because the most basic logic circuit in CMOS, the inverter, uses two transistors in series. NAND gates require three transistors in series, meaning they need a higher voltage than inverters. To accommodate the variability of the process—meaning a wider voltage margin is needed to handle differences between devices—these necessitate the close to 1 volt voltages we see today to ensure operation.
These voltage requirements, coupled with leakage issues, mean that MOSFET miniaturization is increasingly difficult and has no future. If we want to further reduce the voltage to reduce energy consumption, we have two options (neither of which is very attractive): we can reduce the current through the device, which will reduce the startup speed and thus sacrifice performance; or we can maintain a high current level while allowing more current to leak out of the device when it is turned off.
This is where TFETs come in. Unlike raising or lowering the physical energy barrier between the source and drain in a MOSFET, in a TFET we use the gate to control the actual electrical thickness of the energy barrier, thereby controlling the likelihood of electrons passing through the barrier.
The key to this approach lies in the pn junction—but with some twists. In a TFET, the semiconductor material is arranged in a pin and nip configuration. Here, "i" stands for "intrinsic," meaning the channel has as many electrons as holes. The intrinsic state corresponds to the maximum resistivity a semiconductor can possess. It also increases the energy associated with the band structure within the channel, forming a thick energy barrier that charge carriers within the source are unlikely to cross.
Both electrons and holes obey the laws of quantum mechanics, which means their sizes are fuzzy and indeterminate. When the thickness of the energy barrier is less than 10 nanometers, it is unlikely (but not entirely impossible) for an electron that was initially on one side of the barrier to appear on the other side.
In a TFET, we enhance this possibility by applying a voltage to the transistor gate. This causes the conduction band in the source and the valence band in the channel to overlap, opening a tunneling window. It's important to note that in a TFET, electrons tunnel between the conduction and valence bands as they move into the channel. This contrasts sharply with what happens in a MOSFET. In a MOSFET, electrons or holes primarily travel through one band or the other, moving from the source through the channel and finally reaching the drain.
Because the tunneling mechanism is not controlled by carrier flow across the energy barrier, the voltage swing required to start up a TFET can be much smaller than that of a MOSFET. It is sufficient to apply a voltage large enough to create or shift an overlap that allows the conduction and valence bands to cross or not cross. (See illustration "Turn-off and Turn-on").
As a device mechanism, tunneling is not a new concept. Flash memory processors in USB flash drives, mobile phones, and other devices all employ tunneling technology to inject electrons into charge trapping regions on the oxide barrier layer. For example, tunneling junctions used in TFETs are also widely used to connect multijunction solar cells and trigger semiconductor-based quantum cascade lasers. Tunneling also controls how current flows through metal-semiconductor contacts (a crucial part of every semiconductor device).
Research on pn tunneling junctions has also taken some time. This concept was first demonstrated and explained by Nobel laureate Reina Esaki in 1957. However, a fundamental obstacle was encountered in getting the industry to seriously consider how to apply tunneling to logic.
The first paper on TFETs didn't appear until more than a decade ago. At that time, chip manufacturers began to discover that computer clock frequencies were stalling, while also dealing with the heat dissipation problems of increasingly dense and leaky chips.
Joerg Appenzeller and his colleagues at IBM were the first to demonstrate that current swing below the 60 millivolts per decibel limit of MOSFETs was possible. In 2004, they reported the fabrication of a tunneling transistor with a channel made of carbon nanotubes. Its subthreshold swing was only 40 millivolts per decibel. Within a few years, research groups from the University of California, Berkeley, the French microelectronics research institute CEA-LETI, the Belgian inter-university microelectronics center, and Stanford University followed suit. Their research showed that switches with current consumption of less than 60 millivolts per decibel could be manufactured using silicon and germanium, the most important semiconductor materials in the chip industry.
This achievement has greatly excited the industry because, although the current control mechanism of TFETs is a new concept for the semiconductor industry, the device is very similar to MOSFETs. They have the same basic configuration (source, drain, and gate) and produce similar electrical characteristics when connected in a circuit. The fundamental architecture of semiconductor design does not need to be changed.
However, some changes are still necessary. Research shows that silicon and germanium are not very suitable for tunneling. For the same reason, these materials cannot be used to make good light emitters and lasers. Silicon and germanium have indirect band gaps, meaning that in order to transfer from one band to another, electrons must absorb additional energy from the oscillations of the lattice that makes up the material. This additional barrier significantly reduces the likelihood of charge carriers crossing these bands. Therefore, the charge carrying capacity of TFETs made of silicon and germanium is negligible compared to today's transistors.
This is a major obstacle for the industry to adopt this technology. However, mixing elements selected from the third and fifth rows of the periodic table can create a range of direct bandgap materials with a much higher tunneling potential. These materials are not yet used in the mass production of logic chips, but work on integrating them into traditional MOSFETs is accelerating. The idea of using them in logic chips in the foreseeable future no longer seems as far-fetched as it once did.
Research on TFETs made from group III-V elements has also progressed rapidly in recent years. Suman Datta and his colleagues at Pennsylvania State University were the first to demonstrate TFETs made from these elements in 2009. They used a mixture of indium, gallium, and arsenic to create the TFET channel and immediately set a record: the "on" current was up to 50 times that of the best germanium-based TFETs.
Subsequently, teams at Pennsylvania State University and my team at South Bend, Indiana, both developed TFETs that generate higher currents using a mixture of two compounds: aluminum gallium antimonide and indium arsenide. The energy band of the former can be shifted up or down by adjusting the ratio of aluminum to gallium. This allows us to create a tunnel junction that naturally overlaps between the two energy bands, meaning the voltage required to turn on can be reduced. Because the energy barrier can be very thin—about the width of a single atom—more current can pass through. Our device operates well with only 0.5 volts and can carry nearly 200 microamps of current through a 1-millimeter-wide channel, performing comparably to state-of-the-art MOSFETs.
It's important to note that the subthreshold swing of these heterojunction TFETs currently cannot overcome the 60 millivolts per decimal limit of MOSFETs. Many research teams are working to address this challenge. The main bottleneck is the lack of electrons at the interface between the semiconductor and the gate oxide layer—many of these losses are due to loose chemical bonds. These losses trap or prevent charge movement, reducing the amount of charge available for conduction. This means we must apply a higher voltage to the gate to promote the activity of charge carriers within the channel.
Despite this issue, there are reasons for optimism. A team at Intel in Hillsboro, Oregon, and a research team at Hokkaido University in Sapporo, Japan, have demonstrated TFETs for Group III-V elements with subthreshold swings of less than 60 millivolts per decimal. Simulations by the Intel team show that further reducing the subthreshold swing is possible without significant changes to the materials, simply by scaling down their existing transistors. In principle, a subthreshold swing of around 20 millivolts per decimal is possible; the limiting state will be determined by the thermal vibrations of the crystal. These vibrations soften the edges of the conduction and valence bands.
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Just as it was difficult to predict the limits of MOSFETs 50 years ago, it is now very difficult to accurately predict what level TFETs will eventually reach.
One uncertainty is the maximum current a TFET can carry when powered on. The conducting current is the ultimate factor determining the circuit's maximum speed. For a long time, researchers believed the speed wouldn't be very high. However, in 2010, IBM's Siyu Koswatta demonstrated through simulations that gallium antimonide and indium arsenide could potentially carry 1.9 microamps of current per 1 mm wide channel when only 0.4 volts are applied. If this device can be manufactured, it could directly compete with MOSFETs in high-performance applications. The International Technology Roadmap for Semiconductors (ITRS) aims to carry 1.685 microamps of current per 1 mm wide channel at 0.73 volts.
We also need to address the current leakage issue of TFETs in the off state. As the channel becomes shorter, electrons will tunnel directly from the source to the drain more easily.
Determining the ultimate limits of a device depends on several factors, such as electronic structure, deficiencies, and performance requirements. Fortunately, computational tools developed by Purdue University and ETH Zurich now allow researchers to simulate the entire device, including every atom and energy band, to predict its characteristics. This is extremely helpful in guiding experiments.
While the electronic characteristics of TFETs look very promising, some practical problems must be solved before these transistors can be used to manufacture chips. Researchers have focused primarily on developing n-channel TFETs, while p-channel TFETs, and complementary fabrication techniques that can combine these two transistor types to create circuits, have remained on the drawing board.
Furthermore, chip manufacturers must find ways to address the variability problem. As MOSFETs shrink in size, the addition and concentration of dopants, as well as interface roughening, lead to significant variations in electronic properties. When TFETs are introduced, their size will likely be even smaller than MOSFETs. They too will inevitably encounter this problem. For MOSFETs, we must devise alternative parallel approaches, such as redundancy and error correction, to address this issue.
Nevertheless, I remain optimistic about the prospect of even more satisfying results in the future. Only 10 years passed between the development of the first silicon MOSFET and the birth of the first CMOS microprocessor. The leap to TFET may be an even greater challenge, but with our experience accumulated over half a century of semiconductor research, this leap may be achieved sooner than we think.
