There are several hardware approaches for developing EtherCAT bus servo drivers:
(1) Pure bus driver, without pulse, analog, LCD or other peripherals. All instructions and operations are handled through EtherCAT. Possible solutions are: ESC+DSP, FPGA (IP core)+DSP or single FPGA (soft core/hard core + IP). The KPA slave protocol is loaded onto the DSP, soft core or hard core. The difficulty lies in the FPGA IP core and soft core technology, the application and debugging of the FPGA's internal high-speed bus.
(2) Bus + Traditional Driver. This configuration supports both EtherCAT and traditional pulse/analog signals. Possible solutions include: ESC + DSP + FPGA (CPLD), FPGA (IP core) + DSP, and ARM + ESC.
Mainstream ESCs include Beckhoff's ET1100/ET1200, Microchip's LAN9252, and HIS's Netx51/52, among others.
In addition, there are currently some other solutions that integrate CPU and ESC, such as the TIAM335X, Infineon's XMC4800, and Renesas' RZ/T series.
Regardless of the type of EtherCAT servo drive, several important solutions are compared below (only common cases are listed):
Key concepts:
Regarding IP cores: Slave IP cores are also a type of ESC (Electronic Control Controller), essentially a replacement for ET1100/ET1200. The IP core still functions as a slave controller, handling data links, synchronization events, and other hardware events. Even using an IP core to implement ESC only implements the hardware interface function; the software protocol is not loaded. The KPA slave protocol stack is still needed to complete the slave protocol.
Regarding FPGA: To implement FPGA, ESC uses IP Cores to implement EtherCAT functionality and communication. The FMMUs (Fieldbus Memory Management Units), SyncManagers, DCsupport, and PDI are configurable functions.
There are two FPGA implementation methods: one is to integrate an ESC and a soft core uC on the FPGA, and then interact with the main controller using the FPGA's on-chip bus. The other method is to use the FPGA only for the EtherCAT function, and then connect it to an external main controller via an SPI/parallel bus. An FPGA hard core refers to, for example, Xilinx's ZYNQ.
In summary, DSPs, ARMs, and even microcontrollers like the 51 and AVR all belong to the μC category. A slave station consisting of a μC and an ESC is considered a complex slave station (or, in other words, any slave station handling anything other than pure I/O is considered a complex slave station). For the μC to interact with the ESC, it must adhere to the slave protocol in order to read relevant data from the ESC via the PDI interface.
Generally, any slave development process is no longer related to EtherCAT data frames; this task is handled by the ESC. For slave development, you only need to load the slave protocol onto a μC and ensure the communication mechanism between the μC and the ESC is compatible (such as parallel port/SPI). This applies regardless of whether the ESC is a physical ESC device or an IP core.
